公开(公告)号：US12211654B2

公开(公告)日：2025-01-28

申请号：US18048712

申请日：2022-10-21

Applicant: Korea National University of Transportation Industry-Academic Cooperation Foundation

Inventor： Sung Ryong Kim ,  Minh Canh Vu

IPC: H01G4/33 ,  H01G4/012 ,  H01G4/08

Abstract: Disclosed are a high-temperature capacitive energy storage film having a structure in which graphene fluoride (GF) is sandwiched between aramid nanofibers (ANFs) and a method of manufacturing the same.

公开(公告)号：US12100557B2

公开(公告)日：2024-09-24

申请号：US17946630

申请日：2022-09-16

Applicant: TDK CORPORATION

Inventor： Kyohei Takata ,  Shinya Onodera ,  Ken Morita

IPC: H01G4/232 ,  H01G4/08 ,  H01G4/248 ,  H01G4/30

CPC classification number: H01G4/2325 ,  H01G4/08 ,  H01G4/248 ,  H01G4/30

Abstract: An electronic component includes an element body, a plurality of external electrodes on the element body, and an electrical insulator on the element body. Each of the plurality of external electrodes includes a conductive resin layer. The electrical insulator includes an electrical insulating portion located at least on a region between the plurality of external electrodes on a surface of the element body.

公开(公告)号：US20240274654A1

公开(公告)日：2024-08-15

申请号：US18437637

申请日：2024-02-09

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Larry BUFFLE ,  Frédéric Voiron ,  Michal Pomorski ,  Baptiste Truffet

IPC: H01G4/08 ,  H01L21/02

CPC classification number: H01L28/90 ,  H01L21/02376

Abstract: An electrical device that includes a capacitor with a monolithic diamond region having: a diamond substrate; a first electrode layer on the diamond substrate; an intermediate layer on the first electrode layer having a dislocation density comprised between 105.cm −2 to 109.cm−2; and a second electrode layer on the intermediate layer, wherein the first electrode layer and the second electrode layer are doped with p-type impurities and the intermediate layer is doped with a deep level dopant of type n that passivates the dislocations of the intermediate layer, such that the capacitor is formed by the monolithic diamond region between the stack formed by the first electrode layer and the second electrode layer separated by the intermediate layer.

公开(公告)号：US20240213302A1

公开(公告)日：2024-06-27

申请号：US18394644

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin PARK ,  Hanjin LIM ,  Hyungsuk JUNG

IPC: H01G4/08

CPC classification number: H01L28/40 ,  H10B12/315

Abstract: An integrated circuit device may include a transistor on a substrate and a capacitor structure electrically connected to the transistor. The capacitor structure may include a first electrode, a dielectric layer structure on the first electrode, and a second electrode on the dielectric layer structure. The dielectric layer structure may include a plurality of first dielectric layers and a plurality of second dielectric layers that are alternately stacked. The plurality of first dielectric layers may include a ferroelectric material, and the plurality of second dielectric layers may include an anti-ferroelectric material. The distribution proportion of internal defect dipoles gradually may vary in a thickness direction of the dielectric layer structure.

公开(公告)号：US20240178268A1

公开(公告)日：2024-05-30

申请号：US18153375

申请日：2023-01-12

Applicant: Powerchip Semiconductor Manufacturing Corporation

Inventor： Wei-Yu Lin ,  Chuan-Chieh Lin

IPC: H01L23/522 ,  H01G4/08 ,  H01G4/232

CPC classification number: H01L28/75 ,  H01G4/08 ,  H01G4/232 ,  H01L23/5223

Abstract: A capacitor structure including a substrate, a capacitor, a second dielectric layer, a first conductive layer, and a second conductive layer is provided. The capacitor includes first electrode layers, at least one second electrode layer, and a first dielectric layer. The first electrode layers and the at least one second electrode layer are alternately disposed on the substrate. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The second dielectric layer has first openings and at least one second opening. The first openings expose the first electrode layers. The second opening exposes the second electrode layer. The first conductive layer is electrically connected to the first electrode layers. The first conductive layer is a single conductive layer disposed on the second dielectric layer and extending into the first openings. The second conductive layer is electrically connected to the second electrode layer.

公开(公告)号：US20240162280A1

公开(公告)日：2024-05-16

申请号：US18508633

申请日：2023-11-14

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Larry BUFFLE ,  Frédéric VOIRON

IPC: H01G4/08

CPC classification number: H01L28/75 ,  H01L28/91 ,  H01L28/92

Abstract: An electrical device for high-voltage applications and a method for obtaining an electrical device. The electrical device includes a capacitor having: a bottom electrode having a conductive structure, the conductive structure including a base surface and facing protruding walls extending upwards and having a highest surface; a top electrode having at least one conductive region arranged between the facing protruding walls and having a top surface, wherein the top surface of the at least one conductive region lies below or at the level of the highest surface of the protruding walls; and a dielectric region extending conformally over the bottom electrode and surrounding the top electrode, the capacitor being formed by the bottom and top electrodes separated by the dielectric region.

公开(公告)号：US20240111387A1

公开(公告)日：2024-04-04

申请号：US17936456

申请日：2022-09-29

Applicant: Cirque Corporation

Inventor： Brian Monson

IPC: G06F3/044 ,  H01G4/08 ,  H01G4/30 ,  H04B5/00

CPC classification number: G06F3/0443 ,  H01G4/08 ,  H01G4/30 ,  H04B5/0081

Abstract: A capacitance module may include a stack of layers, the stack including a first substrate and at least one capacitance sensing electrode on the substrate. The capacitance module may also include a magnetically conductive, electrically insulating material incorporated into the capacitance module.

公开(公告)号：US20230274882A1

公开(公告)日：2023-08-31

申请号：US18144390

申请日：2023-05-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Kyoung Jin CHA ,  Woo Chul SHIN ,  Seung Heui LEE ,  Beom Seock OH

IPC: H01G4/005 ,  H01G4/08 ,  H01G4/30

CPC classification number: H01G4/005 ,  H01G4/08 ,  H01G4/30

Abstract: A multilayer electronic component includes a body including dielectric layers and internal electrodes alternately disposed in a first direction, and external electrodes disposed on the body to be connected to the internal electrodes. At least one internal electrode of the internal electrodes includes a plurality of disconnected portions penetrating through a respective internal electrode. A disconnected portion of the plurality of disconnected portions includes at least one of a pore or a dielectric substance disposed to connect adjacent dielectric layers to each other. A dielectric filling ratio, defined as a ratio of an overall length of the dielectric substance to an overall length of the disconnected portion on a cross section in the third and first directions, is more than 20% to 80% or less.

公开(公告)号：US20230197770A1

公开(公告)日：2023-06-22

申请号：US17559847

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA

IPC: H01L49/02 ,  H01L23/498 ,  H01G4/33 ,  H01G4/08 ,  H01G4/38

CPC classification number: H01L28/90 ,  H01L23/49822 ,  H01G4/33 ,  H01G4/08 ,  H01G4/38

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to electrically coupled trench capacitors within a substrate. The substrate may be part of an interposer, such as a glass interposer, where the trench capacitors deliver a high capacitance density close to one or more dies that are attached to a surface of the substrate. Portions of the trench capacitor may be a thin film capacitor at a surface of the substrate. The trenches extend from a first side of the substrate toward a second side of the substrate opposite the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US20230141031A1

公开(公告)日：2023-05-11

申请号：US17966744

申请日：2022-10-14

Applicant: HANGZHOU FULLSEMI SEMICONDUCTOR CO., LTD.

Inventor： Wenkang Cao

IPC: H01L49/02 ,  H01G4/08

CPC classification number: H01L28/75 ,  H01G4/08

Abstract: Provided are a semiconductor MIM capacitor device and a method for manufacturing the same. The method includes: providing a substrate, and sequentially forming a bottom electrode layer and a first dielectric layer over the substrate; performing patterning on the first dielectric layer by applying a first mask to form a through hole for the MIM-capacitor disposed in the MIM-capacitor region and through holes for the conductive-plugs disposed in the non-MIM-capacitor region; sequentially forming an interconnection metal layer and a second dielectric layer; performing a surface planarization treatment to remove parts of the interconnection metal layer and the second dielectric layer that are outside the through hole of MIM-capacitor and the conductive plugs; and forming an upper metal layer by applying a second mask on surfaces of the second dielectric layer of the through holes of MIM-capacitor and the conductive plugs.