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公开(公告)号：US20250037759A1
公开(公告)日：2025-01-30
申请号：US18360373
申请日：2023-07-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robin Osa HOEL , Aniruddha PERIYAPATNA NAGENDRA , Prithvi Shankar YEYYADI ANANTHA , Shobhit SINGHAL
IPC: G11C11/413
Abstract: In an example, a system includes an SRAM configured to store a plurality of access control rules, where each rule is stored in a separate row. The SRAM is configured to store a plurality of context entries, where each context entry is stored in a separate row. The system includes a controller configured to receive a request for an access control rule for a memory location from a first context. The controller is configured to search one or more access control rules for the first context, where access control rules for the first context are stored in a binary tree format. The controller is configured to, responsive to finding the access control rule for the memory location, return the access control rule to the first context. The controller is configured to, responsive to not finding the access control rule, return a null notification to the first context.
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公开(公告)号：US20230342292A1
公开(公告)日：2023-10-26
申请号：US17729252
申请日：2022-04-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: G06F12/02
CPC classification number: G06F12/0246 , G06F2212/7201
Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a centralized transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in memory devices associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use, and the technique flexible for different memory hierarchies.
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公开(公告)号：US20230196497A1
公开(公告)日：2023-06-22
申请号：US17556161
申请日：2021-12-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra MODY , Niraj NANDAN , Ankur ANKUR , Mayank MANGLA , Prithvi Shankar YEYYADI ANANTHA
CPC classification number: G06T1/20 , G06T1/60 , G06F11/1004 , G06F9/4812
Abstract: A technique including receiving an image stream for processing; processing the received image stream in a real time mode of operation; outputting an indication that an image processing pipeline has begun processing the received image stream; receiving, in response to the indication, first configuration information associated with test data for testing the image processing pipeline; switching the image processing pipeline to a non-real time mode of operation to process the test data based on the first configuration information during a vertical blanking period of the received image stream; loading the test data from an external memory; switching an input of the image processing pipeline from the image stream to the test data; determining a checksum based on the processed test data; comparing the determined checksum to an expected checksum to determine that the test data was successfully processed; and outputting an indication that the test data was successfully processed.
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公开(公告)号：US20220138058A1
公开(公告)日：2022-05-05
申请号：US17463232
申请日：2021-08-31
Applicant: Texas Instruments Incorporated
Abstract: An electronic device, comprising: a first component configured to transmit a first set of data to a second component by providing a first memory request specifying the first set of data for and an input memory address, and a transaction tracking unit coupled to a first transport interface, the transaction tracking unit configured to: receive the first memory request; transmit a second memory request that specifies at least a first portion of the first set of data, via the first transport interface, to the second component; receive a response to the second memory request from the second component; determine that the response corresponds to the second memory request; and provide, to the first component, an output response based on the received response to the second memory request.
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