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公开(公告)号:US20240214511A1
公开(公告)日:2024-06-27
申请号:US18599324
申请日:2024-03-08
Applicant: Texas Instruments Incorporated
Inventor: Mihir Narendra MODY , Brijesh JADAV , Gang HUA , Niraj NANDAN , Rajasekhar Reddy ALLU , Ankur ANKUR , Mayank MANGLA
CPC classification number: H04N5/2628 , G06T3/40 , G06T7/12 , G06T7/60 , G06T11/00
Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.
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公开(公告)号:US20230196497A1
公开(公告)日:2023-06-22
申请号:US17556161
申请日:2021-12-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra MODY , Niraj NANDAN , Ankur ANKUR , Mayank MANGLA , Prithvi Shankar YEYYADI ANANTHA
CPC classification number: G06T1/20 , G06T1/60 , G06F11/1004 , G06F9/4812
Abstract: A technique including receiving an image stream for processing; processing the received image stream in a real time mode of operation; outputting an indication that an image processing pipeline has begun processing the received image stream; receiving, in response to the indication, first configuration information associated with test data for testing the image processing pipeline; switching the image processing pipeline to a non-real time mode of operation to process the test data based on the first configuration information during a vertical blanking period of the received image stream; loading the test data from an external memory; switching an input of the image processing pipeline from the image stream to the test data; determining a checksum based on the processed test data; comparing the determined checksum to an expected checksum to determine that the test data was successfully processed; and outputting an indication that the test data was successfully processed.
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公开(公告)号:US20240428365A1
公开(公告)日:2024-12-26
申请号:US18826385
申请日:2024-09-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra MODY , Niraj NANDAN , Ankur ANKUR , Mayank MANGLA , Prithvi Shankar YEYYADI ANANTHA
Abstract: A technique including receiving an image stream for processing; processing the received image stream in a real time mode of operation; outputting an indication that an image processing pipeline has begun processing the received image stream; receiving, in response to the indication, first configuration information associated with test data for testing the image processing pipeline; switching the image processing pipeline to a non-real time mode of operation to process the test data based on the first configuration information during a vertical blanking period of the received image stream; loading the test data from an external memory; switching an input of the image processing pipeline from the image stream to the test data; determining a checksum based on the processed test data; comparing the determined checksum to an expected checksum to determine that the test data was successfully processed; and outputting an indication that the test data was successfully processed.
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公开(公告)号:US20240427717A1
公开(公告)日:2024-12-26
申请号:US18819007
申请日:2024-08-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra MODY , Ankur ANKUR , Vivek Vilas DHANDE , Kedar Satish CHITNIS , Niraj NANDAN , Brijesh JADAV , Shyam JAGANNATHAN , Prithvi Shankar YEYYADI ANANTHA , Santhanakrishnan Narayanan NARAYANAN
Abstract: Systems and methods in which trace data is efficiently managed are provided. An example system includes a memory, a first interface, and a processing resource communicably coupled to the first interface and to the memory. The processing resource includes a buffer, and a first controller to transmit a set of data from the buffer with associated trace information for the set of data to the memory. A second controller transmits the set of data with the associated trace information from the memory to a second interface.
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公开(公告)号:US20230291864A1
公开(公告)日:2023-09-14
申请号:US17690829
申请日:2022-03-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra MODY , Brijesh JADAV , Gang HUA , Niraj NANDAN , Rajasekhar Reddy ALLU , Ankur ANKUR , Mayank MANGLA
CPC classification number: H04N5/2628 , G06T3/40 , G06T7/12 , G06T7/60 , G06T11/00
Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.
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公开(公告)号:US20230267084A1
公开(公告)日:2023-08-24
申请号:US17677638
申请日:2022-02-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra MODY, JR. , Ankur ANKUR , Vivek Vilas DHANDE , Kedar Satish CHITNIS , Niraj NANDAN , Brijesh JADAV , Shyam JAGANNATHAN , Prithvi Shankar YEYYADI ANANTHA , Santhanakrishnan Narayanan NARAYANAN
CPC classification number: G06F13/28 , G06F13/1673 , G06F13/4221 , G06F15/7807 , G06F9/4881
Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.
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