公开(公告)号：US20230386907A1

公开(公告)日：2023-11-30

申请号：US17751976

申请日：2022-05-24

Applicant: Texas Instruments Incorporated

Inventor： Qi-Zhong Hong ,  Joseph Jian Song ,  Gregory Boyd Shinn ,  Bhaskar Srinivasan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76829 ,  H01L23/5226 ,  H01L23/53238 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76877

Abstract: An electronic device includes a semiconductor die having a multilevel metallization structure including stacked levels with respective dielectric layers and metal lines, and a low leakage, low hydrogen diffusion barrier layer on one of the stacked levels. The diffusion barrier layer contacts a side of the dielectric layer and the metal line of the one of the stacked levels, and the diffusion barrier layer includes silicon nitride material having a first bond percentage ratio of ammonia to silicon nitride that is greater than a second bond percentage ratio of silicon hydride to silicon nitride.

公开(公告)号：US20230154915A1

公开(公告)日：2023-05-18

申请号：US17525167

申请日：2021-11-12

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Qi-Zhong Hong ,  Jarvis Benjamin Jacobs

IPC: H01L27/01 ,  H01L23/522 ,  H01L27/13

CPC classification number: H01L27/016 ,  H01L23/5228 ,  H01L27/13 ,  H01L27/1207

Abstract: An electronic device includes a first thin film resistor and a second thin film resistor above a dielectric layer that extends in a first plane of orthogonal first and second directions, the first resistor has three portions with the second portion extending between the first and third portions, and a recess etched into the top side of the second portion by a controlled etch process to increase the sheet resistance of the first resistor for dual thin film resistor integration.

公开(公告)号：US11424183B2

公开(公告)日：2022-08-23

申请号：US16995288

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qi-Zhong Hong ,  Honglin Guo ,  Benjamin James Timmer ,  Gregory Boyd Shinn

IPC: H01L23/522 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.

公开(公告)号：US20210343642A1

公开(公告)日：2021-11-04

申请号：US17378203

申请日：2021-07-16

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US10784193B2

公开(公告)日：2020-09-22

申请号：US16047889

申请日：2018-07-27

Applicant: Texas Instruments Incorporated

Inventor： Qi-Zhong Hong ,  Honglin Guo ,  Benjamin James Timmer ,  Gregory Boyd Shinn

IPC: H01L23/52 ,  H01L23/522 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.

公开(公告)号：US10439020B2

公开(公告)日：2019-10-08

申请号：US15855635

申请日：2017-12-27

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Shih Chang Chang

IPC: H01L49/02 ,  H01L21/3213 ,  H01L27/01

Abstract: A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.

公开(公告)号：US20190295948A1

公开(公告)日：2019-09-26

申请号：US16423723

申请日：2019-05-28

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US10242147B2

公开(公告)日：2019-03-26

申请号：US15452259

申请日：2017-03-07

Applicant: Texas Instruments Incorporated

Inventor： Qi-Zhong Hong

IPC: H01L21/44 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528

Abstract: A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.