公开(公告)号：US20230386907A1

公开(公告)日：2023-11-30

申请号：US17751976

申请日：2022-05-24

Applicant: Texas Instruments Incorporated

Inventor： Qi-Zhong Hong ,  Joseph Jian Song ,  Gregory Boyd Shinn ,  Bhaskar Srinivasan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L21/76829 ,  H01L23/5226 ,  H01L23/53238 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76877

Abstract: An electronic device includes a semiconductor die having a multilevel metallization structure including stacked levels with respective dielectric layers and metal lines, and a low leakage, low hydrogen diffusion barrier layer on one of the stacked levels. The diffusion barrier layer contacts a side of the dielectric layer and the metal line of the one of the stacked levels, and the diffusion barrier layer includes silicon nitride material having a first bond percentage ratio of ammonia to silicon nitride that is greater than a second bond percentage ratio of silicon hydride to silicon nitride.

公开(公告)号：US11424183B2

公开(公告)日：2022-08-23

申请号：US16995288

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qi-Zhong Hong ,  Honglin Guo ,  Benjamin James Timmer ,  Gregory Boyd Shinn

IPC: H01L23/522 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.

公开(公告)号：US10784193B2

公开(公告)日：2020-09-22

申请号：US16047889

申请日：2018-07-27

Applicant: Texas Instruments Incorporated

Inventor： Qi-Zhong Hong ,  Honglin Guo ,  Benjamin James Timmer ,  Gregory Boyd Shinn

IPC: H01L23/52 ,  H01L23/522 ,  H01L49/02

Abstract: An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.