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    CONTAMINATION DETECTION METHOD
    2.
    发明公开
    CONTAMINATION DETECTION METHOD 审中-公开

    公开(公告)号：US20230378005A1

    公开(公告)日：2023-11-23

    申请号：US17746655

    申请日：2022-05-17

    Applicant: Texas Instruments Incorporated

    Inventor： Honglin Guo ,  Robert M. Higgins

    IPC: H01L21/66

    CPC classification number: H01L22/34

    Abstract: A method of forming an integrated circuit on a substrate is described herein. The method includes forming a first doped region of a detection structure on the substrate, the first doped region comprises a first doped conductivity type. The method forming a capacitor of the detection structure, which includes forming a second doped region of a second conductivity type opposite the first doped conductivity type, the second doped region surrounded by the first doped region. The second doped well comprises a top surface area smaller than a top surface area of the first doped region. The method includes performing parametric testing on the capacitor over a plurality of breakdown voltages. The method includes determining the gate oxide integrity of the capacitor based on the parametric testing over the plurality of breakdown voltages.

    Heated capacitor and method of forming the heated capacitor
    6.
    发明授权
    Heated capacitor and method of forming the heated capacitor 有权
    加热电容器和形成加热电容器的方法

    公开(公告)号：US09293254B2

    公开(公告)日：2016-03-22

    申请号：US14288433

    申请日：2014-05-28

    Applicant: Texas Instruments Incorporated

    Inventor： Honglin Guo ,  Byron Lovell Williams

    IPC: H01L21/02 ,  H01G2/08 ,  H01G4/18 ,  H01B3/30

    CPC classification number: H01G2/08 ,  H01B3/306 ,  H01G4/018 ,  H01G4/18 ,  H01G4/33 ,  H01G4/40 ,  Y10T29/42

    Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.

    Abstract translation: 加热的电容器通过下金属板，上金属板，位于下金属板附近的下金属迹线，位于上金属板附近的上金属迹线或两个下金属迹线， 位于邻近上金属板的下金属板和上金属迹线附近，以从电阻产生热量以从湿敏绝缘层去除水分。

    Device with isolation barrier and fault detection
    8.
    发明授权
    Device with isolation barrier and fault detection 有权

    公开(公告)号：US10992293B2

    公开(公告)日：2021-04-27

    申请号：US16137146

    申请日：2018-09-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Xiong Li ,  William Toth ,  Honglin Guo ,  Danyang Zhu

    IPC: H03K17/08 ,  H03K17/081

    Abstract: A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.

    RELIABLE LATERAL FLUX CAPACITOR DESIGN
    9.
    发明申请
    RELIABLE LATERAL FLUX CAPACITOR DESIGN 有权

    公开(公告)号：US20210098394A1

    公开(公告)日：2021-04-01

    申请号：US17034435

    申请日：2020-09-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Honglin Guo

    IPC: H01L23/64 ,  H01L27/01 ,  H01L21/82

    Abstract: A semiconductor device includes an impedance having a first port and a second port located over a semiconductor substrate. The impedance includes at least one metal-insulator-metal (MIM) lateral flux capacitor (LFC) pair. Each LFC pair includes a first LFC connected in series with a second LFC. A terminal of the first LFC is connected to the first port, and a terminal of the second LFC is connected to the second port. Optionally the device further includes circuitry formed over the semiconductor substrate, wherein the circuitry is configured to implement a circuit function in cooperation with the impedance.

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