公开(公告)号：US09628787B2

公开(公告)日：2017-04-18

申请号：US14607053

申请日：2015-01-27

Applicant: Texas Instruments Incorporated

Inventor： Rahul Gulati ,  Vasant Easwaran ,  Mihir Narendra Mody ,  Prashant Dinkar Karandikar ,  Prithvi Y. A. Shankar ,  Aishwarya Dubey ,  Kedar Chitnis ,  Rajat Sagar

IPC: H04N17/00 ,  H04N17/02 ,  G06T7/00

CPC classification number: H04N17/002 ,  G06T7/0002 ,  G06T2207/30168 ,  G06T2207/30252

Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.

公开(公告)号：US20230350819A1

公开(公告)日：2023-11-02

申请号：US18345098

申请日：2023-06-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1668 ,  G06F13/28

Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.

公开(公告)号：US11693795B2

公开(公告)日：2023-07-04

申请号：US17138740

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/28

Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.

公开(公告)号：US20210326276A1

公开(公告)日：2021-10-21

申请号：US17138740

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Mihir Mody ,  Rajat Sagar

IPC: G06F13/16 ,  G06F13/28

Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.

公开(公告)号：US11027656B1

公开(公告)日：2021-06-08

申请号：US16709548

申请日：2019-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Sagar ,  Mihir Narendra Mody ,  Anthony Joseph Lell ,  Gregory Raymond Shurtz

IPC: H04N21/2343 ,  B60R1/00 ,  H04N5/225

Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.

公开(公告)号：US20150304648A1

公开(公告)日：2015-10-22

申请号：US14607053

申请日：2015-01-27

Applicant: Texas Instruments Incorporated

Inventor： Rahul Gulati ,  Vasant Easwaran ,  Mihir Narendra Mody ,  Prashant Dinkar Karandikar ,  Prithvi Y.A. Shankar ,  Aishwarya Dubey ,  Kedar Chitnis ,  Rajat Sagar

IPC: H04N17/00 ,  G06T7/00

CPC classification number: H04N17/002 ,  G06T7/0002 ,  G06T2207/30168 ,  G06T2207/30252

Abstract: A method for testing an imaging subsystem of a system-on-a-chip (SOC) is provided that includes executing imaging subsystem test software instructions periodically on a processor of the SOC, receiving reference image data in the imaging subsystem responsive to the executing of the test software instructions, performing image signal processing on the reference image data by the imaging subsystem to generate processed reference image data, and using the processed reference image data by the test software instructions to verify whether or not the imaging subsystem is operating correctly.

Abstract translation: 提供了一种用于测试片上系统（SOC）的成像子系统的方法，其包括在所述SOC的处理器上周期性地执行成像子系统测试软件指令，响应于所述成像子系统的执行而接收所述成像子系统中的参考图像数据 测试软件指令，由成像子系统对参考图像数据执行图像信号处理，以生成经处理的参考图像数据，以及通过测试软件指令使用经处理的参考图像数据来验证成像子系统是否正确地操作。