公开(公告)号：US11447071B2

公开(公告)日：2022-09-20

申请号：US17340207

申请日：2021-06-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rajat Sagar ,  Mihir Narendra Mody ,  Anthony Joseph Lell ,  Gregory Raymond Shurtz

IPC: B60R1/00 ,  H04N5/225

Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.

公开(公告)号：US10949357B2

公开(公告)日：2021-03-16

申请号：US16256821

申请日：2019-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Gregory Raymond Shurtz ,  Mihir Narendra Mody ,  Charles Lance Fuoco ,  Donald E. Steiss ,  Jonathan Elliot Bergsagel ,  Jason A. T. Jones

IPC: G06F12/1027 ,  G06F9/455 ,  G06F12/1036

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US10929209B2

公开(公告)日：2021-02-23

申请号：US16377404

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US20240126560A1

公开(公告)日：2024-04-18

申请号：US18395697

申请日：2023-12-25

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A.T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  G06F13/28 ,  H04L45/00 ,  H04L47/32 ,  H04L49/351

CPC classification number: G06F9/4418 ,  G06F9/4406 ,  G06F13/28 ,  H04L45/54 ,  H04L45/66 ,  H04L47/32 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US11880333B2

公开(公告)日：2024-01-23

申请号：US17314313

申请日：2021-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jason A. T. Jones ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  Kishon Vijay Abraham Israel Vijayponraj ,  Bradley Douglas Cobb ,  Sanand Prasad ,  Gregory Raymond Shurtz ,  Martin Jeffrey Ambrose ,  Jayant Thakur

IPC: G06F15/78 ,  G06F13/10

CPC classification number: G06F15/7807 ,  G06F13/10 ,  G06F15/7864

Abstract: An integrated circuit. The integrated circuit comprises an interconnect communication bus and a plurality of peripheral component interconnect (PCI) multi-function endpoints (MFN-EPs) coupled to the interconnect communication bus, each PCI MFN-EP comprising a multiplexing device, a first address translation unit (ATU), and at least one PCI function circuit, each PCI function circuit comprising another ATU and a plurality of base address registers (BARs).

公开(公告)号：US20230244557A1

公开(公告)日：2023-08-03

申请号：US18132683

申请日：2023-04-10

Applicant: Texas Instruments Incorporated

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

CPC classification number: G06F9/546 ,  G06F9/5027 ,  G06F9/3836 ,  G06F9/45558 ,  G06F9/4806 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US10540736B2

公开(公告)日：2020-01-21

申请号：US15668453

申请日：2017-08-03

Applicant: Texas Instruments Incorporated

Inventor： Sunita Nadampalli ,  Anish Reghunath ,  Brian Okchon Chae ,  Jonathan Elliot Bergsagel ,  Gregory Raymond Shurtz

IPC: G06T1/20 ,  G06F3/06 ,  G06F9/54 ,  H04N21/4143 ,  H04N5/44

Abstract: An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.

公开(公告)号：US11960416B2

公开(公告)日：2024-04-16

申请号：US17558278

申请日：2021-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Brad Wu ,  Abhishek Shankar ,  Mihir Narendra Mody ,  Gregory Raymond Shurtz ,  Jason A. T. Jones ,  Hemant Vijay Kumar Hariyani

IPC: G06F13/16

CPC classification number: G06F13/1647

Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

公开(公告)号：US11693787B2

公开(公告)日：2023-07-04

申请号：US17171185

申请日：2021-02-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Gregory Raymond Shurtz ,  Mihir Narendra Mody ,  Charles Lance Fuoco ,  Donald E. Steiss ,  Jonathan Elliot Bergsagel ,  Jason A.T. Jones

IPC: G06F12/1027 ,  G06F9/455

CPC classification number: G06F12/1027 ,  G06F9/45558 ,  G06F2009/45583 ,  G06F2212/657

Abstract: In an example, a device includes a memory and a processor core coupled to the memory via a memory management unit (MMU). The device also includes a system MMU (SMMU) cross-referencing virtual addresses (VAs) with intermediate physical addresses (IPAs) and IPAs with physical addresses (PAs). The device further includes a physical address table (PAT) cross-referencing IPAs with each other and cross-referencing PAs with each other. The device also includes a peripheral virtualization unit (PVU) cross-referencing IPAs with PAs, and a routing circuit coupled to the memory, the SMMU, the PAT, and the PVU. The routing circuit is configured to receive a request comprising an address and an attribute and to route the request through at least one of the SMMU, the PAT, or the PVU based on the address and the attribute.

公开(公告)号：US11656925B2

公开(公告)日：2023-05-23

申请号：US17138036

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

CPC classification number: G06F9/546 ,  G06F9/3836 ,  G06F9/45558 ,  G06F9/4806 ,  G06F9/5027 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.