FAULT DETECTION AND METHOD OF DETECTING FAULTS IN DIGITAL IMAGING SYSTEMS
    1.
    发明申请
    FAULT DETECTION AND METHOD OF DETECTING FAULTS IN DIGITAL IMAGING SYSTEMS 有权
    故障检测和数字成像系统故障检测方法

    公开(公告)号:US20160119617A1

    公开(公告)日:2016-04-28

    申请号:US14521751

    申请日:2014-10-23

    Inventor: Rajat Sagar

    CPC classification number: H04N17/002 H04N5/23222 H04N5/238

    Abstract: A method of analyzing a digital camera includes generating first image data using an image sensor in the camera. A first analysis is performed on at least one portion of the first image data. Second image data is generated using the image sensor and a second analysis is performed on the at least one portion of the second image data. The results of the first analysis are compared to the results of the second analysis. A signal indicating a fault with the digital camera is generated in response to the first analysis differing from the second analysis by a predetermined amount.

    Abstract translation: 分析数码相机的方法包括使用相机中的图像传感器生成第一图像数据。 对第一图像数据的至少一部分执行第一分析。 使用图像传感器生成第二图像数据,并且对第二图像数据的至少一部分执行第二分析。 将第一次分析的结果与第二次分析的结果进行比较。 响应于与第二分析不同的第一分析预定量产生指示数字照相机故障的信号。

    Reconfigurable image processing hardware pipeline

    公开(公告)号:US11276134B2

    公开(公告)日:2022-03-15

    申请号:US16847864

    申请日:2020-04-14

    Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.

    Safe execution in place (XIP) from flash memory

    公开(公告)号:US10388392B2

    公开(公告)日:2019-08-20

    申请号:US15482729

    申请日:2017-04-08

    Abstract: A device is provided that includes a processor, a flash memory configured to store error correcting code (ECC) blocks for execution in place (XIP) processing by the processor, wherein an ECC block includes a data block and an ECC code for the data block, a flash interface controller coupled to the flash memory, and an error correcting code (ECC) engine coupled between the processor and the flash interface controller, wherein the ECC engine is configured to receive a read command for the flash memory from the processor, to translate a read address to an ECC block address, to read the ECC block at the ECC block address from the flash memory via the flash interface controller, and to verify the ECC code in the read ECC block.

    Safe Execution in Place (XIP) From Flash Memory

    公开(公告)号:US20180293129A1

    公开(公告)日:2018-10-11

    申请号:US15482729

    申请日:2017-04-08

    CPC classification number: G11C16/3459 G06F11/1068 G11C29/42

    Abstract: A device is provided that includes a processor, a flash memory configured to store error correcting code (ECC) blocks for execution in place (XIP) processing by the processor, wherein an ECC block includes a data block and an ECC code for the data block, a flash interface controller coupled to the flash memory, and an error correcting code (ECC) engine coupled between the processor and the flash interface controller, wherein the ECC engine is configured to receive a read command for the flash memory from the processor, to translate a read address to an ECC block address, to read the ECC block at the ECC block address from the flash memory via the flash interface controller, and to verify the ECC code in the read ECC block.

    Fault detection and method of detecting faults in digital imaging systems
    7.
    发明授权
    Fault detection and method of detecting faults in digital imaging systems 有权
    数字成像系统故障检测及故障检测方法

    公开(公告)号:US09525865B2

    公开(公告)日:2016-12-20

    申请号:US14521751

    申请日:2014-10-23

    Inventor: Rajat Sagar

    CPC classification number: H04N17/002 H04N5/23222 H04N5/238

    Abstract: A method of analyzing a digital camera includes generating first image data using an image sensor in the camera. A first analysis is performed on at least one portion of the first image data. Second image data is generated using the image sensor and a second analysis is performed on the at least one portion of the second image data. The results of the first analysis are compared to the results of the second analysis. A signal indicating a fault with the digital camera is generated in response to the first analysis differing from the second analysis by a predetermined amount.

    Abstract translation: 分析数码相机的方法包括使用相机中的图像传感器生成第一图像数据。 对第一图像数据的至少一部分执行第一分析。 使用图像传感器生成第二图像数据,并且对第二图像数据的至少一部分执行第二分析。 将第一次分析的结果与第二次分析的结果进行比较。 响应于与第二分析不同的第一分析预定量产生指示数字照相机故障的信号。

    Methods and apparatus to extend local buffer of a hardware accelerator

    公开(公告)号:US12050542B2

    公开(公告)日:2024-07-30

    申请号:US18345098

    申请日:2023-06-30

    CPC classification number: G06F13/1668 G06F13/28

    Abstract: Methods and apparatus to extend local buffer of a hardware accelerator are disclosed herein. In some examples, an apparatus, including a local memory, a first hardware accelerator (HWA), a second HWA, the second HWA and the first HWA connected in a flexible data pipeline, and a spare scheduler to manage, in response to the spare scheduler inserted in the flexible data pipeline, data movement between the first HWA and the second HWA through the local memory and a memory. Local buffer extension may be performed by software to control data movement between local memory and other system memory. The other system memory may be on-chip memory and/or external memory. The HWA sub-system includes a set of spare schedulers to manage the data movement. Data aggregation may be performed in the other system memory. Additionally, the other system memory may be utilized for conversion between data line and data block.

    Flexible hub for handling multi-sensor data

    公开(公告)号:US11447071B2

    公开(公告)日:2022-09-20

    申请号:US17340207

    申请日:2021-06-07

    Abstract: A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.

    Sparse optical flow support in an optical flow system

    公开(公告)号:US10380746B2

    公开(公告)日:2019-08-13

    申请号:US15784285

    申请日:2017-10-16

    Abstract: An optical flow system includes a binary mask generation circuit and an optical flow circuit. The binary mask generation circuit is configured to receive a plurality of points of interest from a captured image that contains an array of pixels arranged as rows and columns and includes width lines that correspond to the rows and height lines that correspond to the columns. The binary mask generation circuit is also configured to generate a binary mask based on the plurality of points of interest. The binary mask includes a representation of a subset of the plurality of points of interest. The optical flow circuit is configured to receive the binary mask and generate an optical flow map of the subset of the plurality of points of interest.

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