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公开(公告)号：US20180254780A1
公开(公告)日：2018-09-06
申请号：US15911141
申请日：2018-03-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Callaghan Taft , Alexander Bodem
CPC classification number: H03M1/203 , H03F3/19 , H03F3/45475 , H03F2200/451 , H03M1/1245 , H03M1/445
Abstract: A circuit including an amplifier array including an amplifier stage with M amplifiers (M≥2), connected to a resistor interpolator (interpolation order N≥2) including an input row and at least a second row, each row comprising interpolation resistors connected in series at nodes. The input row including M driven nodes connected to a respective amplifier, and connected in parallel to the second row, with at least some first-row interpolation nodes connected to corresponding second-row interpolation nodes. The resistor interpolator comprising at least one multi-row interpolation cell, with: in the input row, a driven node coupled through first and second interpolation resistors to respective adjacent first and second interpolation nodes; and in the second row, third and fourth interpolation nodes coupled through third and fourth interpolation resistors to an intermediate fifth interpolation node; and with the first and second interpolation nodes connected respectively to the third and fourth interpolation nodes.
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Patent Agency Ranking
公开(公告)号：US20180253122A1
公开(公告)日：2018-09-06
申请号：US15911138
申请日：2018-03-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Paul Joseph Kramer , Matthew Hansen Childs , Robert Callaghan Taft
Abstract: Clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock with active and inactive clock edges within a clock period, and signal capture circuitry to capture repetitive signal transitions at an active clock edge, based on pre-defined setup and hold times which determine a setup/hold window. Clock phase adjustment circuitry is configured to adjust clock phase so that the repetitive signal transitions occur within a signal capture window between setup/hold windows. Clock phase adjustment can be based on: aligning the clock inactive edges to the repetitive signal transitions; and/or averaging successive phase comparisons of the clock and the repetitive signal transitions; and/or selectively performing an initial polarity inversion to generate a polarity inverted clock, and then adjusting clock phase of the polarity inverted clock. An example implementation is JESD204B (subclass1) to adjust DEVCLK phase relative to a SYSREF timing reference control signal.
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公开(公告)号：US20210026397A1
公开(公告)日：2021-01-28
申请号：US16935240
申请日：2020-07-22
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.
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公开(公告)号：US10833663B2
公开(公告)日：2020-11-10
申请号：US16509526
申请日：2019-07-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Schultz , Robert Callaghan Taft
Abstract: A circuit comprises a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port; a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters.
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公开(公告)号：US10775833B2
公开(公告)日：2020-09-15
申请号：US15911138
申请日：2018-03-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Paul Joseph Kramer , Matthew Hansen Childs , Robert Callaghan Taft
Abstract: Clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock with active and inactive clock edges within a clock period, and signal capture circuitry to capture repetitive signal transitions at an active clock edge, based on pre-defined setup and hold times which determine a setup/hold window. Clock phase adjustment circuitry is configured to adjust clock phase so that the repetitive signal transitions occur within a signal capture window between setup/hold windows. Clock phase adjustment can be based on: aligning the clock inactive edges to the repetitive signal transitions; and/or averaging successive phase comparisons of the clock and the repetitive signal transitions; and/or selectively performing an initial polarity inversion to generate a polarity inverted clock, and then adjusting clock phase of the polarity inverted clock. An example implementation is JESD204B (subclass1) to adjust DEVCLK phase relative to a SYSREF timing reference control signal.
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公开(公告)号：US10396768B2
公开(公告)日：2019-08-27
申请号：US15951973
申请日：2018-04-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Schultz , Robert Callaghan Taft
Abstract: A circuit comprises a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port; a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters.
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