公开(公告)号：US11443889B2

公开(公告)日：2022-09-13

申请号：US16903618

申请日：2020-06-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dushmantha Bandara Rajapaksha ,  Roland Sperlich ,  Anant Shankar Kamath ,  Vijayalakshmi Devarajan ,  Wesley Ray

IPC: H02M3/155 ,  H01F27/28 ,  H04L13/02 ,  H02M1/42

Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.

公开(公告)号：US10298238B2

公开(公告)日：2019-05-21

申请号：US15600378

申请日：2017-05-19

Applicant: Texas Instruments Incorporated

Inventor： Weicheng Zhang ,  Huanzhang Huang ,  Yanli Fan ,  Roland Sperlich

IPC: H03K17/16 ,  H03K19/0944 ,  H03K19/0185

Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.

公开(公告)号：US09130792B2

公开(公告)日：2015-09-08

申请号：US14299187

申请日：2014-06-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Roland Sperlich ,  Huanzhang Huang ,  Charles M. Branch

IPC: H03K5/159 ,  H04L25/02 ,  H04B3/14

CPC classification number: H04L27/01 ,  H04B3/144 ,  H04L25/026 ,  H04L25/03019 ,  H04L25/03885

Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

Abstract translation: 公开了串行通信电路（图3）。 电路包括均衡器电路（306），其布置成接收数据信号（CH 1）并产生均衡的数据信号。 对数检测器电路（300）接收数据信号并产生指示数据信号的功率电平的功率信号。 判定电路（332）接收电力信号并产生选择信号。 第一选择电路（336）接收多个第一校正信号，并且响应于选择信号将第一校正信号中的一个施加到均衡器电路。