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公开(公告)号：US20140362900A1
公开(公告)日：2014-12-11
申请号：US14299187
申请日：2014-06-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Roland Sperlich , Huanzhang Huang , Charles M. Branch
IPC: H04L27/01
CPC classification number: H04L27/01 , H04B3/144 , H04L25/026 , H04L25/03019 , H04L25/03885
Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.
Abstract translation: 公开了串行通信电路（图3）。 电路包括均衡器电路（306），其布置成接收数据信号（CH 1）并产生均衡的数据信号。 对数检测器电路（300）接收数据信号并产生指示数据信号的功率电平的功率信号。 判定电路（332）接收电力信号并产生选择信号。 第一选择电路（336）接收多个第一校正信号，并且响应于选择信号将第一校正信号中的一个施加到均衡器电路。
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公开(公告)号：US09602318B2
公开(公告)日：2017-03-21
申请号：US14819239
申请日：2015-08-05
Applicant: Texas Instruments Incorporated
Inventor： Roland Sperlich , Huanzhang Huang , Charles M. Branch
CPC classification number: H04L27/01 , H04B3/144 , H04L25/026 , H04L25/03019 , H04L25/03885
Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.
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Patent Agency Ranking
3.发明申请Logical to Multi-Variable-Record Connect Element to Interface Logical Signals Between Analog and Digital Simulations 审中-公开逻辑到多变量记录连接元件到模拟和数字模拟之间的接口逻辑信号公开(公告)号：US20170024504A1
公开(公告)日：2017-01-26
申请号：US15215773
申请日：2016-07-21
Applicant: Texas Instruments Incorporated
Inventor： Charles M. Branch
IPC: G06F17/50
CPC classification number: G06F17/5036 , G06F17/5022
Abstract: In described examples, embodiments include a circuit simulator having a processor and a memory. The memory stores at least one digital circuit element definition. The memory also stores at least one analog circuit element definition. The memory also stores at least one connect element definition, the connect element definition having at least one input coupled to the output of the digital circuit element definition and at least one output coupled to the analog circuit definition. The connect element definition includes at least a first current source coupled to the at least one output and a first impedance coupled to the at least one output, a signal on the at least one input determining the value of the first impedance.
Abstract translation: 在所描述的示例中，实施例包括具有处理器和存储器的电路模拟器。 存储器存储至少一个数字电路元件定义。 存储器还存储至少一个模拟电路元件定义。 存储器还存储至少一个连接元件定义，连接元件定义具有耦合到数字电路元件定义的输出的至少一个输入和耦合到模拟电路定义的至少一个输出。 连接元件定义包括耦合到至少一个输出的至少第一电流源和耦合到至少一个输出的第一阻抗，该至少一个输入上的信号确定第一阻抗的值。
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公开(公告)号：US09130792B2
公开(公告)日：2015-09-08
申请号：US14299187
申请日：2014-06-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Roland Sperlich , Huanzhang Huang , Charles M. Branch
CPC classification number: H04L27/01 , H04B3/144 , H04L25/026 , H04L25/03019 , H04L25/03885
Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.
Abstract translation: 公开了串行通信电路（图3）。 电路包括均衡器电路（306），其布置成接收数据信号（CH 1）并产生均衡的数据信号。 对数检测器电路（300）接收数据信号并产生指示数据信号的功率电平的功率信号。 判定电路（332）接收电力信号并产生选择信号。 第一选择电路（336）接收多个第一校正信号，并且响应于选择信号将第一校正信号中的一个施加到均衡器电路。
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公开(公告)号：US10423277B2
公开(公告)日：2019-09-24
申请号：US15499290
申请日：2017-04-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Srinath Hosur , Ashish Khandelwal , Charles M. Branch
Abstract: A circuit includes a receiver that includes an input stage to receive a touch signal from a touch system. A noise reduction circuit that samples the touch signal to detect a noise signal in the touch signal. The noise reduction circuit generates a reduction signal based on the noise signal that is fed back to the input stage of the receiver to mitigate noise interference of the noise signal with respect to the touch signal at the receiver.
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公开(公告)号：US20150341194A1
公开(公告)日：2015-11-26
申请号：US14819239
申请日：2015-08-05
Applicant: Texas Instruments Incorporated
Inventor： Roland Sperlich , Huanzhang Huang , Charles M. Branch
CPC classification number: H04L27/01 , H04B3/144 , H04L25/026 , H04L25/03019 , H04L25/03885
Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.
Abstract translation: 公开了串行通信电路（图3）。 电路包括均衡器电路（306），其布置成接收数据信号（CH 1）并产生均衡的数据信号。 对数检测器电路（300）接收数据信号并产生指示数据信号的功率电平的功率信号。 判定电路（332）接收电力信号并产生选择信号。 第一选择电路（336）接收多个第一校正信号，并且响应于选择信号将第一校正信号中的一个施加到均衡器电路。
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公开(公告)号：US09154133B2
公开(公告)日：2015-10-06
申请号：US13630721
申请日：2012-09-28
Applicant: Texas Instruments Incorporated
Inventor： Muhammad Yusuf Ali , Rajkumar Sankaralingam , Charles M. Branch
IPC: H03H9/46 , H03K19/003 , H02H9/04 , H01L27/02
CPC classification number: H03K19/00384 , H01L27/0266 , H02H9/046
Abstract: An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.
Abstract translation: 逆变器型电平移位器包括第一电源电压和第一接地电压。 第一逆变器对第一电源电压和第一接地电压进行操作以产生第一逆变器输出。 第一反相器包括第一PMOS晶体管，其具有耦合到阻塞PMOS晶体管的源极的漏极和具有耦合到阻塞NMOS晶体管的源极的漏极的第一NMOS晶体管。 电平移位器还包括第二电源电压和第二接地电压，以及第二反相器，耦合到第一反相器输出并对第二电源电压和第二接地电压进行操作。 阻塞PMOS在第一电源电压的第二电源电压中的电压尖峰的事件上提供所需的阻塞，并且阻塞NMOS晶体管相对于第二电源电压在第二接地电压中的电压尖峰的事件上提供所需的阻塞 第一接地电压。
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