公开(公告)号：US09087917B2

公开(公告)日：2015-07-21

申请号：US14022317

申请日：2013-09-10

Applicant: Texas Instruments Incorporated

Inventor： Chet Vernon Lenox ,  Seung-Chul Song ,  Brian K. Kirkpatrick

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

Abstract translation: 通过去除牺牲栅极电介质层和牺牲栅极以形成栅极腔来形成集成电路。 在栅腔中形成保形电介质第一衬垫，并且在第一衬垫上形成共形第二衬垫。 第一蚀刻从栅极腔的底部去除第二衬垫，使第二衬垫的材料留在栅腔的侧壁上。 第二蚀刻从第二衬垫暴露的栅腔的底部去除第一衬垫，在栅腔的侧壁上的第二衬垫下方留下第一衬垫的底部上的第一衬垫的底部的材料。 第三蚀刻从栅极腔去除第二衬垫，在栅极腔中留下第一衬里的L形间隔物。 永久性栅极介电层和置换栅极形成在栅极腔中。

公开(公告)号：US20140315361A1

公开(公告)日：2014-10-23

申请号：US14325787

申请日：2014-07-08

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Seung-Chul Song

IPC: H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0928

Abstract: A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.