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    Inner L-spacer for replacement gate flow
    2.
    发明授权
    Inner L-spacer for replacement gate flow 有权
    内部L型间隔器用于更换浇口流

    公开(公告)号：US09087917B2

    公开(公告)日：2015-07-21

    申请号：US14022317

    申请日：2013-09-10

    Applicant: Texas Instruments Incorporated

    Inventor： Chet Vernon Lenox ,  Seung-Chul Song ,  Brian K. Kirkpatrick

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8234 ,  H01L27/092

    CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

    Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

    Abstract translation: 通过去除牺牲栅极电介质层和牺牲栅极以形成栅极腔来形成集成电路。 在栅腔中形成保形电介质第一衬垫，并且在第一衬垫上形成共形第二衬垫。 第一蚀刻从栅极腔的底部去除第二衬垫，使第二衬垫的材料留在栅腔的侧壁上。 第二蚀刻从第二衬垫暴露的栅腔的底部去除第一衬垫，在栅腔的侧壁上的第二衬垫下方留下第一衬垫的底部上的第一衬垫的底部的材料。 第三蚀刻从栅极腔去除第二衬垫，在栅极腔中留下第一衬里的L形间隔物。 永久性栅极介电层和置换栅极形成在栅极腔中。

    System for controlling SiGe-to-gate spacing
    5.
    发明授权
    System for controlling SiGe-to-gate spacing 有权
    用于控制SiGe到栅极间距的系统

    公开(公告)号：US08828833B1

    公开(公告)日：2014-09-09

    申请号：US14031738

    申请日：2013-09-19

    Applicant: Texas Instruments Incorporated

    Inventor： James Walter Blatchford ,  Chet Vernon Lenox

    IPC: H01L21/336 ,  H01L21/66 ,  H01L21/306

    CPC classification number: H01L21/30604 ,  H01L22/12 ,  H01L22/20 ,  H01L29/66636 ,  H01L29/78

    Abstract: A method of forming PMOS transistors. A SiGe cavity formation process includes cavity etching a structure including a gate stack having a gate electrode on a gate dielectric on a substrate, a sidewall spacer, and a hardmask layer on the gate electrode. The cavity etching includes (i) a first anisotropic dry etch for etching through the hardmask layer lateral to the gate stack and beginning a recessed cavity in the substrate, (ii) a dry lateral etch, and (iii) a second anisotropic dry etch. A wet crystallographic etch completes formation of the recessed cavity. A customized time is calculated for a selected dry etch step from the plurality of dry etch steps based on in-process SiGe cavity data for a measured cavity parameter for a SiGe cavity formation process. The customized time for the selected dry etch is used to cavity etch at least one substrate in a lot or run.

    Abstract translation: 一种形成PMOS晶体管的方法。 SiGe腔形成工艺包括腔体蚀刻包括栅极叠层的结构，栅极叠层在栅电极上的栅极电介质上具有栅电极，侧壁间隔物和硬掩模层。 空腔蚀刻包括（i）用于蚀刻穿过栅堆叠横向的硬掩模层的第一各向异性干蚀刻，并且在衬底中开始凹陷腔，（ii）干侧向蚀刻，和（iii）第二各向异性干蚀刻。 湿式结晶蚀刻完成了凹腔的形成。 基于用于SiGe空腔形成过程的测量空腔参数的基于工艺SiGe腔数据，从多个干蚀刻步骤中选择干蚀刻步骤的定制时间。 所选择的干蚀刻的定制时间用于在大量或运行中对至少一个衬底进行腔蚀刻。

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