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公开(公告)号：US20230065567A1
公开(公告)日：2023-03-02
申请号：US17461495
申请日：2021-08-30
Applicant: Texas Instruments Incorporated
Inventor： Shailendra Kumar Baranwal , Yogesh Kumar Ramadass , Yinglai Xia
Abstract: Described embodiments include an audio amplifier circuit that includes a first amplifier having a differential first amplifier input adapted to be coupled to an audio input source, a multiplexer having first and second mux inputs, a control input and a mux output. The first mux input is coupled to the differential amplifier output. There is a signal generator having a generator input coupled to the mux output. There is also a driver circuit having a driver circuit input and a driver circuit output, the driver circuit input coupled to the generator output, and a second amplifier having a first error input coupled to a current sense terminal that is configured to provide a voltage proportional to a current supplied from a power supply terminal, and a second error input coupled to a current limit terminal configured to provide a reference voltage proportional to a current limit value.
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公开(公告)号：US10281946B1
公开(公告)日：2019-05-07
申请号：US15996917
申请日：2018-06-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shailendra Kumar Baranwal , Anant Shankar Kamath
IPC: G05F3/26 , H03K19/003 , H03K19/0185 , H03F3/16
Abstract: A bandgap voltage reference is provided in quasi-parallel with a resistor in the input path of a digital input circuit. Because of the quasi-parallel nature, the current used by the digital input circuit is limited to an amount based on the value of the external resistor. The input current is split between circuitry used to provide the logic signal across the selected isolation barrier and a sink transistor so that the current remains constant. This allows the digital input circuit to accurately limit input current without needing field-side power.
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公开(公告)号：US20190089261A1
公开(公告)日：2019-03-21
申请号：US15859005
申请日：2017-12-29
Applicant: Texas Instruments Incorporated
Inventor： Maurizio Granato , Giavanni Frattini , Shailendra Kumar Baranwal
CPC classification number: H02M3/33592 , H02M1/088 , H02M3/337 , H02M2001/0054 , H02M2001/0058
Abstract: In described examples, an isolated DC-DC converter includes: an input node for receiving an input voltage; a transformer including a primary side having first and second terminals and a primary side ground; and first and second low-side switches. The first low-side switch is coupled between the first terminal and the primary side ground. The second low-side switch is coupled between the second terminal and the primary side ground. A first voltage is across the first low-side switch, and a second voltage is across the second low-side switch. Also, the isolated DC-DC converter includes first and second high-side switches. The first high-side switch is coupled between the first terminal and the input node and is configured to be activated by a voltage at the second terminal. The second high-side switch is coupled between the second terminal and the input node and is configured to be activated by a voltage at the first terminal. Further, the isolated DC-DC converter includes a switch controller to cause the first and second voltages to alternatingly be zero by opening and closing the first and second low-side switches, as follows. The first low-side switch is closed when the first voltage is zero. During a first phase, the first low-side switch is opened at a time to enable a current through the primary side to charge the first terminal to the input voltage while discharging the second terminal to reduce the second voltage to zero. The second low-side switch is closed when the second voltage is zero. During a second phase, the second low-side switch is opened at a time to enable the current through the primary side to charge the second terminal to the input voltage while discharging the first terminal to reduce the first voltage to zero.
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公开(公告)号：US20240413800A1
公开(公告)日：2024-12-12
申请号：US18808183
申请日：2024-08-19
Applicant: Texas Instruments Incorporated
Inventor： Shailendra Kumar Baranwal , Yogesh Kumar Ramadass , Yinglai Xia
Abstract: Described embodiments include an audio amplifier circuit that includes a first amplifier having a differential first amplifier input adapted to be coupled to an audio input source, a multiplexer having first and second mux inputs, a control input and a mux output. The first mux input is coupled to the differential amplifier output. There is a signal generator having a generator input coupled to the mux output. There is also a driver circuit having a driver circuit input and a driver circuit output, the driver circuit input coupled to the generator output, and a second amplifier having a first error input coupled to a current sense terminal that is configured to provide a voltage proportional to a current supplied from a power supply terminal, and a second error input coupled to a current limit terminal configured to provide a reference voltage proportional to a current limit value.
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Patent Agency Ranking
公开(公告)号：US12095429B2
公开(公告)日：2024-09-17
申请号：US17461495
申请日：2021-08-30
Applicant: Texas Instruments Incorporated
Inventor： Shailendra Kumar Baranwal , Yogesh Kumar Ramadass , Yinglai Xia
CPC classification number: H03F3/2171 , H03F1/0205 , H04R3/00 , H03F2200/03
Abstract: Described embodiments include an audio amplifier circuit that includes a first amplifier having a differential first amplifier input adapted to be coupled to an audio input source, a multiplexer having first and second mux inputs, a control input and a mux output. The first mux input is coupled to the differential amplifier output. There is a signal generator having a generator input coupled to the mux output. There is also a driver circuit having a driver circuit input and a driver circuit output, the driver circuit input coupled to the generator output, and a second amplifier having a first error input coupled to a current sense terminal that is configured to provide a voltage proportional to a current supplied from a power supply terminal, and a second error input coupled to a current limit terminal configured to provide a reference voltage proportional to a current limit value.
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公开(公告)号：US11356082B2
公开(公告)日：2022-06-07
申请号：US17119604
申请日：2020-12-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yinglai Xia , Shailendra Kumar Baranwal , Yogesh Kumar Ramadass , Junmin Jiang
Abstract: A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.
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公开(公告)号：US10601332B2
公开(公告)日：2020-03-24
申请号：US15859005
申请日：2017-12-29
Applicant: Texas Instruments Incorporated
Inventor： Maurizio Granato , Giovanni Frattini , Shailendra Kumar Baranwal
Abstract: In described examples, an isolated DC-DC converter includes: an input node for receiving an input voltage; a transformer including first and second terminals; first and second low-side switches; and first and second high-side switches. The first low-side switch is coupled between the first terminal and a primary side ground. The second low-side switch is coupled between the second terminal and the primary side ground. The first high-side switch is coupled between the first terminal and the input node and is configured to be activated by a voltage at the second terminal. The second high-side switch is coupled between the second terminal and the input node and is configured to be activated by a voltage at the first terminal. Further, the isolated DC-DC converter includes a switch controller to cause the first and second voltages to alternatingly be zero by opening and closing the first and second low-side switches.
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公开(公告)号：US20190089263A1
公开(公告)日：2019-03-21
申请号：US15859145
申请日：2017-12-29
Applicant: Texas Instruments Incorporated
Inventor： Maurizio Granato , Giavanni Frattini , Shailendra Kumar Baranwal
Abstract: In described examples, an isolated DC-DC converter includes an input node for receiving an input voltage, and a transformer including a primary side having first and second terminals and a ground. First and second high-side switches are coupled between the input node and the first and second terminals, respectively. A first low-side switch is coupled between the first terminal and the ground, and through a first voltage limiter to be activated by a voltage at the second terminal. A second low-side switch is coupled between the second terminal and the ground, and through a second voltage limiter to be activated by a voltage at the first terminal A switch controller controls the high-side switches so that voltages across the high-side switches are alternatingly zero, using a current through the primary side to alternatingly charge one terminal to an input voltage and discharge the other terminal to a ground voltage.
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公开(公告)号：US10090769B2
公开(公告)日：2018-10-02
申请号：US15363188
申请日：2016-11-29
Applicant: Texas Instruments Incorporated
Inventor： Shailendra Kumar Baranwal , Maurizio Granato , Giovanni Frattini
Abstract: An electronic device, which includes an H-bridge circuit and a miniaturized transformer that is coupled to operate at VHF frequency, and a driver circuit for an n-type power transistor of the H-bridge circuit are disclosed. The driver circuit includes a first p-type transistor and an n-type transistor coupled between an upper rail and a lower rail, with an output taken between the drains of the first p-type transistor and the n-type transistor being coupled to a gate of the n-type power transistor. The driver circuit also includes a sample-and-hold capacitor coupled to capture a drain voltage for the first n-type power transistor on a first edge of a control signal for the first n-type power transistor and a comparator coupled to compare the captured drain voltage to a lower rail on a given edge of a clock signal and to provide a comparator value. The driver circuit also includes an up/down counter, which is coupled to receive the comparator value, to adjust a counter value responsive to receiving the comparator value and to output the counter value, and a first timing circuit that is coupled to receive the counter value and to send an adjustable pulse towards a gate of the first p-type transistor and a gate of the n-type transistor.
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