公开(公告)号：US20210183683A1

公开(公告)日：2021-06-17

申请号：US17184553

申请日：2021-02-24

Applicant: Texas Instruments Incorporated

Inventor： Matthew John Sherbin ,  Michael Todd Wyant ,  Dave Charles Stepniak ,  Sada Hiroyuki ,  Shoichi Iriguchi ,  Genki Yano

IPC: H01L21/683 ,  H01L21/687

Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.

公开(公告)号：US10763230B2

公开(公告)日：2020-09-01

申请号：US16228962

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Yi Yan ,  Hau Nguyen

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L23/495

Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

公开(公告)号：US10658240B1

公开(公告)日：2020-05-19

申请号：US16291995

申请日：2019-03-04

Applicant: Texas Instruments Incorporated

Inventor： Shoichi Iriguchi ,  Hiroyuki Sada ,  Genki Yano

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  B23K26/364 ,  B23K101/40

Abstract: In a described example, a method includes: forming stress induced dislocations along scribe lanes between semiconductor dies on a semiconductor wafer using a laser; mounting a first side of the semiconductor wafer on the first side of a first dicing tape; removing a backgrinding tape from the semiconductor wafer; attaching a second dicing tape to a second side of the semiconductor wafer opposite the first side, the second dicing tape adhering to portions of the first dicing tape that are spaced from the semiconductor wafer, forming a dual taped wafer dicing assembly; separating the semiconductor dies by stretching the first dicing tape and stretching the second dicing tape; removing the second dicing tape from the semiconductor dies; and removing the semiconductor dies from the first dicing tape.