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    PACKAGE FOR STRESS SENSITIVE COMPONENT AND SEMICONDUCTOR DEVICE
    1.
    发明申请
    PACKAGE FOR STRESS SENSITIVE COMPONENT AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230005881A1

    公开(公告)日：2023-01-05

    申请号：US17364769

    申请日：2021-06-30

    Applicant: Texas Instruments Incorporated

    Inventor： Anindya Poddar ,  Mahmud Chowdhury ,  Hau Nguyen ,  Masamitsu Matsuura ,  Ting-Ta Yen

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

    Abstract: In a described example, an apparatus includes: a first semiconductor die with a component on a first surface; a second semiconductor die mounted on a package substrate and having a third surface facing away from the package substrate; a solder seal bonded to and extending from the first surface of the first semiconductor die flip chip mounted to the third surface of the second semiconductor die, the solder seal at least partially surrounding the stress sensitive component; a first solder joint formed between the solder seal and the third surface of the second semiconductor die; a second solder joint formed between solder at an end of the post connect and the third surface of the second semiconductor die; and a mold compound covering the second surface of the first semiconductor die, a portion of the second semiconductor die, and an outside periphery of the solder seal.

    FLIP CHIP PACKAGED DEVICES WITH THERMAL PAD
    2.
    发明申请
    FLIP CHIP PACKAGED DEVICES WITH THERMAL PAD 有权

    公开(公告)号：US20230005880A1

    公开(公告)日：2023-01-05

    申请号：US17364735

    申请日：2021-06-30

    Applicant: Texas Instruments Incorporated

    Inventor： Anindya Poddar ,  Ashok Surendra Prabhu ,  Hau Nguyen ,  Kurt Edward Sincerbox ,  Makoto Shibuya

    IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48

    Abstract: In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

    OPEN CAVITY PACKAGE USING CHIP-EMBEDDING TECHNOLOGY
    4.
    发明申请
    OPEN CAVITY PACKAGE USING CHIP-EMBEDDING TECHNOLOGY 有权
    使用芯片嵌入技术的开放封装

    公开(公告)号：US20170015548A1

    公开(公告)日：2017-01-19

    申请号：US14963362

    申请日：2015-12-09

    Applicant: Texas Instruments Incorporated

    Inventor： Jie Mao ,  Hau Nguyen ,  Luu Nguyen ,  Anindya Poddar

    IPC: B81C1/00 ,  B81B7/00

    CPC classification number: B81C1/00873 ,  B81B7/007 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2201/0292 ,  B81B2201/047 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00333 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0159 ,  B81C2201/0181 ,  B81C2201/0188 ,  B81C2203/0136 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/19 ,  H01L2221/68359 ,  H01L2224/04105 ,  H01L2224/96 ,  H01L2924/3511

    Abstract: A method for fabricating packaged semiconductor devices (100) with an open cavity (110a) in panel format; placing (process 201) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad (230) and symmetrically placed vertical pillars (231); attaching (process 202) semiconductor chips (101) with sensor systems face-down onto the tape; laminating (process 203) and thinning (process 204) low CTE insulating material (234) to fill gaps between chips and grid; turning over (process 205) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process 206) uniform metal layer across assembly and optionally plating (process 209) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process 212) insulating stiffener across panel; opening (process 213) cavities in stiffener to access the sensor system; and singulating (process 214) packaged devices by cutting metallic pieces.

    Abstract translation: 一种以面板格式制造具有开口腔（110a）的封装半导体器件（100）的方法; 将具有平垫（230）和对称放置的垂直柱（231）的金属片的面板尺寸网格放置（处理201）在粘合剂载带上。 将具有传感器系统的半导体芯片（工艺202）面朝下地附接到带上; 层压（工艺203）和减薄（工艺204）低CTE绝缘材料（234）以填充芯片和网格之间的间隙; 翻转（过程205）组装以去除胶带; 等离子体清洁组件正面，溅射和图案化（工艺206）跨组合均匀的金属层和任选的电镀（工艺209）金属层以形成重新布线迹线和扩展的接触垫用于组装; 层压（工艺212）跨板的绝缘加强件; 在加强件中打开（过程213）空腔以接近传感器系统; 并通过切割金属片来分割（处理214）包装的装置。

    WAFER LEVEL PROCESSING FOR MICROELECTRONIC DEVICE PACKAGE WITH CAVITY
    6.
    发明申请
    WAFER LEVEL PROCESSING FOR MICROELECTRONIC DEVICE PACKAGE WITH CAVITY 有权

    公开(公告)号：US20230092132A1

    公开(公告)日：2023-03-23

    申请号：US17950027

    申请日：2022-09-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Hau Nguyen ,  Anindya Poddar

    IPC: B81B3/00 ,  H01L23/00 ,  B81C3/00

    Abstract: A described example includes: a MEMS component on a device side surface of a first semiconductor substrate; a second semiconductor substrate bonded to the device side surface of the first semiconductor substrate by a first seal patterned to form sidewalls that surround the MEMS component; a third semiconductor substrate having a second seal extending from a surface and bonded to the backside surface of the first semiconductor substrate by the second seal, the second seal forming sidewalls of a gap beneath the MEMS component. A trench extends through the first semiconductor substrate and at least partially surrounds the MEMS component. The third semiconductor substrate is mounted on a package substrate. A bond wire or ribbon bond couples the bond pad to a conductive lead on the package substrate; and mold compound covers the MEMS component, the bond wire, and a portion of the package substrate.

    Semiconductor systems having premolded dual leadframes
    9.
    发明授权
    Semiconductor systems having premolded dual leadframes 有权

    公开(公告)号：US10312184B2

    公开(公告)日：2019-06-04

    申请号：US14932055

    申请日：2015-11-04

    Applicant: Texas Instruments Incorporated

    Inventor： Rajeev D. Joshi ,  Hau Nguyen ,  Anindya Poddar ,  Ken Pham

    IPC: H01L23/495 ,  H01L21/48 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

    Abstract: A dual leadframe (100) for semiconductor systems comprising a first leadframe (110) having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe (120) having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions (150) in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material (140) filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

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