公开(公告)号：US11021786B2

公开(公告)日：2021-06-01

申请号：US16209513

申请日：2018-12-04

Applicant: Texas Instruments Incorporated

Inventor： Luu Thanh Nguyen ,  Mahmud Halim Chowdhury ,  Ashok Prabhu ,  Anindya Poddar

IPC: H01L21/3205 ,  C23C14/12 ,  C23F11/10 ,  H01L21/288 ,  H01L21/768

Abstract: In a described example, a method for passivating a copper structure includes: passivating a surface of the copper structure with a copper corrosion inhibitor layer; and depositing a protection overcoat layer with a thickness less than 35 μm on a surface of the copper corrosion inhibitor layer.

公开(公告)号：US20200043878A1

公开(公告)日：2020-02-06

申请号：US16053199

申请日：2018-08-02

Applicant: Texas Instruments Incorporated

Inventor： Daiki Komatsu ,  Makoto Shibuya ,  Yi Yan ,  Hau Nguyen ,  Luu Thanh Nguyen ,  Anindya Poddar

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure.

公开(公告)号：US11450638B2

公开(公告)日：2022-09-20

申请号：US17009648

申请日：2020-09-01

Applicant: Texas Instruments Incorporated

Inventor： Dibyajat Mishra ,  Ashok Prabhu ,  Tomoko Noguchi ,  Luu Thanh Nguyen ,  Anindya Poddar ,  Makoto Yoshino ,  Hau Nguyen

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31

Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

公开(公告)号：US10763231B2

公开(公告)日：2020-09-01

申请号：US16047888

申请日：2018-07-27

Applicant: Texas Instruments Incorporated

Inventor： Dibyajat Mishra ,  Ashok Prabhu ,  Tomoko Noguchi ,  Luu Thanh Nguyen ,  Anindya Poddar ,  Makoto Yoshino ,  Hau Nguyen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

公开(公告)号：US10650957B1

公开(公告)日：2020-05-12

申请号：US16176630

申请日：2018-10-31

Applicant: Texas Instruments Incorporated

Inventor： Yi Yan ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar

IPC: H01F27/26 ,  H01F27/40 ,  H01L23/495 ,  H01L23/00 ,  H01F27/28 ,  H01F41/24 ,  H01L23/66 ,  H01L23/31

Abstract: Apparatus to form a transformer, an inductor, a capacitor or other passive electronic component, with patterned conductive features in a lamination structure, and one or more ferrite sheets or other magnetic core structures attached to the lamination structure via one or more inkjet printed magnetic adhesive layers that join the magnetic core structure or structures to the lamination structure.

公开(公告)号：US11367699B2

公开(公告)日：2022-06-21

申请号：US17009664

申请日：2020-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Yi Yan ,  Hau Nguyen

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/495

Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

公开(公告)号：US11031311B2

公开(公告)日：2021-06-08

申请号：US16197413

申请日：2018-11-21

Applicant: Texas Instruments Incorporated

Inventor： Luu Thanh Nguyen

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/02 ,  H01L23/00 ,  H01L23/495

Abstract: In a described example, a packaged semiconductor device includes: a semiconductor die with a component proximate to a surface of the semiconductor die; the semiconductor die mounted on a substrate. The component is covered with a first polymer layer with a first modulus and at least a portion of the first polymer layer is covered by at least one second polymer layer with a second modulus and the second modulus is greater than the first modulus. The semiconductor die and a portion of the substrate are covered with mold compound.

公开(公告)号：US20210351098A1

公开(公告)日：2021-11-11

申请号：US17317795

申请日：2021-05-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luu Thanh Nguyen

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/78 ,  H01L21/02

Abstract: In a described example, a packaged semiconductor device includes: a semiconductor die with a component proximate to a surface of the semiconductor die; the semiconductor die mounted on a substrate. The component is covered with a first polymer layer with a first modulus and at least a portion of the first polymer layer is covered by at least one second polymer layer with a second modulus and the second modulus is greater than the first modulus. The semiconductor die and a portion of the substrate are covered with mold compound.

公开(公告)号：US10763230B2

公开(公告)日：2020-09-01

申请号：US16228962

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Yi Yan ,  Hau Nguyen

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L23/495

Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

公开(公告)号：US20200161205A1

公开(公告)日：2020-05-21

申请号：US16197413

申请日：2018-11-21

Applicant: Texas Instruments Incorporated

Inventor： Luu Thanh Nguyen

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/78 ,  H01L21/02

Abstract: In a described example, a packaged semiconductor device includes: a semiconductor die with a component proximate to a surface of the semiconductor die; the semiconductor die mounted on a substrate. The component is covered with a first polymer layer with a first modulus and at least a portion of the first polymer layer is covered by at least one second polymer layer with a second modulus and the second modulus is greater than the first modulus. The semiconductor die and a portion of the substrate are covered with mold compound.