公开(公告)号：US11171031B2

公开(公告)日：2021-11-09

申请号：US16041888

申请日：2018-07-23

Applicant: Texas Instruments Incorporated

Inventor： Matthew John Sherbin ,  Michael Todd Wyant ,  Dave Charles Stepniak ,  Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano

IPC: H01L21/683 ,  B28D5/00 ,  H01L21/78 ,  H01L21/687

Abstract: A die matrix expander includes a subring including ≥3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter

公开(公告)号：US10665475B2

公开(公告)日：2020-05-26

申请号：US14301942

申请日：2014-06-11

Applicant: Texas Instruments Incorporated

Inventor： Dan Okamoto ,  Hiroyuki Sada

IPC: H01L21/56 ,  H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

公开(公告)号：US20200251352A1

公开(公告)日：2020-08-06

申请号：US16853186

申请日：2020-04-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dan Okamoto ,  Hiroyuki Sada

IPC: H01L21/56 ,  H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

公开(公告)号：US11367699B2

公开(公告)日：2022-06-21

申请号：US17009664

申请日：2020-09-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Yi Yan ,  Hau Nguyen

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/495

Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

公开(公告)号：US20150364373A1

公开(公告)日：2015-12-17

申请号：US14301942

申请日：2014-06-11

Applicant: Texas Instruments Incorporated

Inventor： Dan Okamoto ,  Hiroyuki Sada

IPC: H01L21/78 ,  H01L23/28 ,  H01L21/56 ,  H01L23/495

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

Abstract translation: 一种四边形扁平无铅（“QFN”）封装，其包括具有基本上位于第一平面中的有源侧的管芯和基本上位于平行于第一平面的第二平面中的背面; 多个单独的导电焊盘，其各自具有基本位于所述第一平面中的第一侧和基本位于所述第二平面中的第二侧; 以及位于导电垫和模具之间的空隙中的第一和第二平面之间的模具复合体。 另外，制造多个QFN封装的方法包括：形成嵌入有多个管芯的塑料材料条和多个导线焊盘，所述多个导体焊盘被引线接合到管芯上，并通过切割将所述条带分割成多个QFN封装 只有塑料材质。

公开(公告)号：US11735435B2

公开(公告)日：2023-08-22

申请号：US16853186

申请日：2020-04-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dan Okamoto ,  Hiroyuki Sada

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L21/561 ,  H01L23/3157 ,  H01L23/49541 ,  H01L23/49805 ,  H01L23/49861 ,  H01L24/97 ,  H01L23/3107 ,  H01L23/5389 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A quad flat no lead (“QFN”) package that includes a die having an active side positioned substantially in a first plane and a backside positioned substantially in a second plane parallel to the first plane; a plurality of separate conductive pads each having a first side positioned substantially in the first plane and a second side positioned substantially in the second plane; and mold compound positioned between the first and second planes in voids between the conductive pads and the dies. Also a method of producing a plurality of QFN packages includes forming a strip of plastic material having embedded therein a plurality of dies and a plurality of conductive pads that are wire bonded to the dies and singulating the strip into a plurality of QFN packages by cutting through only the plastic material.

公开(公告)号：US11664276B2

公开(公告)日：2023-05-30

申请号：US16205692

申请日：2018-11-30

Applicant: Texas Instruments Incorporated

Inventor： Matthew John Sherbin ,  Michael Todd Wyant ,  Christopher Daniel Manack ,  Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano ,  Ming Zhu ,  Joseph O. Liu

IPC: H01L23/544 ,  H01L21/78 ,  B23K26/364 ,  H01L23/00 ,  H01L21/268

CPC classification number: H01L21/78 ,  B23K26/364 ,  H01L21/268 ,  H01L23/562

Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.

公开(公告)号：US10763230B2

公开(公告)日：2020-09-01

申请号：US16228962

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hiroyuki Sada ,  Shoichi Iriguchi ,  Genki Yano ,  Luu Thanh Nguyen ,  Ashok Prabhu ,  Anindya Poddar ,  Yi Yan ,  Hau Nguyen

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L23/495

Abstract: A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

公开(公告)号：US10658240B1

公开(公告)日：2020-05-19

申请号：US16291995

申请日：2019-03-04

Applicant: Texas Instruments Incorporated

Inventor： Shoichi Iriguchi ,  Hiroyuki Sada ,  Genki Yano

IPC: H01L21/78 ,  H01L21/683 ,  H01L23/00 ,  H01L21/56 ,  B23K26/364 ,  B23K101/40

Abstract: In a described example, a method includes: forming stress induced dislocations along scribe lanes between semiconductor dies on a semiconductor wafer using a laser; mounting a first side of the semiconductor wafer on the first side of a first dicing tape; removing a backgrinding tape from the semiconductor wafer; attaching a second dicing tape to a second side of the semiconductor wafer opposite the first side, the second dicing tape adhering to portions of the first dicing tape that are spaced from the semiconductor wafer, forming a dual taped wafer dicing assembly; separating the semiconductor dies by stretching the first dicing tape and stretching the second dicing tape; removing the second dicing tape from the semiconductor dies; and removing the semiconductor dies from the first dicing tape.