公开(公告)号：US11301248B2

公开(公告)日：2022-04-12

申请号：US16878603

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Timothy David Anderson ,  Soujanya Narnur

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F7/487 ,  G06F7/499 ,  G06F7/24 ,  H03H17/06 ,  G06F7/53 ,  G06F9/48 ,  G06F7/57

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.

公开(公告)号：US12124728B2

公开(公告)日：2024-10-22

申请号：US18353181

申请日：2023-07-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Soujanya Narnur

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/80

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1668 ,  G06F15/8076

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

公开(公告)号：US11704046B2

公开(公告)日：2023-07-18

申请号：US17722477

申请日：2022-04-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Soujanya Narnur

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/80

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1668 ,  G06F15/8076

Abstract: A method of clearing of registers and logic designs with AND and OR logics to propagate the zero values provided to write enable signal buses upon the execution of clear instruction of more than one registers, allowing more than one architecturally visible registers to be cleared with one signal instruction regardless of the values of data buses.

公开(公告)号：US20220206802A1

公开(公告)日：2022-06-30

申请号：US17690344

申请日：2022-03-09

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Timothy David Anderson ,  Soujanya Narnur

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06F7/487 ,  G06F7/499 ,  G06F7/24 ,  H03H17/06 ,  G06F7/53 ,  G06F9/48 ,  G06F7/57

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.

公开(公告)号：US20220156072A1

公开(公告)日：2022-05-19

申请号：US17588416

申请日：2022-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Soujanya Narnur ,  Timothy David Anderson ,  Mujibur Rahman ,  Duc Quang Bui

IPC: G06F9/30 ,  H03H17/06 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/38 ,  G06F9/48 ,  G06F17/16 ,  G06F7/24

Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

公开(公告)号：US10936317B2

公开(公告)日：2021-03-02

申请号：US16422324

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Joseph Zbiciak ,  Sahithi Krishna ,  Soujanya Narnur

IPC: G06F12/02 ,  G06F9/30 ,  G06F12/0811

Abstract: A digital signal processor having at least one streaming address generator, each with dedicated hardware, for generating addresses for writing multi-dimensional streaming data that comprises a plurality of elements. Each at least one streaming address generator is configured to generate a plurality of offsets to address the streaming data, and each of the plurality of offsets corresponds to a respective one of the plurality of elements. The address of each of the plurality of elements is the respective one of the plurality of offsets combined with a base address.

公开(公告)号：US20200371799A1

公开(公告)日：2020-11-26

申请号：US16878611

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Soujanya Narnur ,  Timothy David Anderson ,  Mujibur Rahman ,  Duc Quang Bui

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.

公开(公告)号：US20200371797A1

公开(公告)日：2020-11-26

申请号：US16878603

申请日：2020-05-20

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Timothy David Anderson ,  Soujanya Narnur

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/487

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.