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公开(公告)号：US20240004663A1
公开(公告)日：2024-01-04
申请号：US18370487
申请日：2023-09-20
CPC分类号： G06F9/3802 , G06F9/3836 , G06F9/3887 , G06F9/3001 , G06F9/30036 , G06F9/30079 , G06F9/30145
摘要： An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.
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公开(公告)号：US11829300B2
公开(公告)日：2023-11-28
申请号：US17958503
申请日：2022-10-03
IPC分类号： G06F7/06 , G06F12/1045 , G06F9/30 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , H03H17/06 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009 , G06F15/78
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/3016 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3818 , G06F9/3836 , G06F9/3851 , G06F9/3867 , G06F9/3887 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/781 , G06F15/7807 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.
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公开(公告)号：US20230350813A1
公开(公告)日：2023-11-02
申请号：US18348047
申请日：2023-07-06
IPC分类号： G06F12/1045 , G06F9/30 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , H03H17/06 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009
CPC分类号： G06F12/1045 , G06F9/30145 , G06F9/345 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/1048 , G06F9/30065 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30021 , G06F9/30149 , G06F9/3818 , G06F9/3836 , G06F9/3851 , G06F9/48 , G06F17/16 , G06F9/30032 , G06F9/30072 , G06F9/3887 , H03H17/0664 , G06F9/3855 , G06F9/30098 , G06F9/3016 , G06F9/32 , G06F9/3802 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009 , G06F11/10 , G06F9/3822 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F15/7807
摘要： Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication unit. Each of these multiplication units includes carry-save adder circuitry with a respective outputs, partial product alignment multiplexing logic coupled to the outputs of the associated carry-save adder circuitry. The processor further comprises communication paths coupled between the outputs of the carry-save adder circuitry of the first multiplication unit and the partial product alignment multiplexing logic of the second multiplication unit. In other configurations, each of the first and second multiplication units may include one or more instances of masking logic, one or more instances of a multiplier array coupled to the associated instance(s) of masking logic, and one or more instances of a multiplexer set coupled to the associated instance(s) of multiplier array(s). Each of multiplexer set instance(s) of a particular multiplication unit is coupled to the carry-save adder circuitry of that multiplication unit.
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公开(公告)号：US11734194B2
公开(公告)日：2023-08-22
申请号：US17713002
申请日：2022-04-04
IPC分类号： G06F9/30 , G06F12/1045 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F7/24 , G06F7/487 , G06F7/499 , G06F7/53 , G06F7/57 , G06F9/48 , G06F17/16 , H03H17/06 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009 , G06F15/78
CPC分类号： G06F12/1045 , G06F7/24 , G06F7/487 , G06F7/4876 , G06F7/49915 , G06F7/53 , G06F7/57 , G06F9/3001 , G06F9/30014 , G06F9/3016 , G06F9/30021 , G06F9/30032 , G06F9/30036 , G06F9/30065 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/383 , G06F9/3818 , G06F9/3836 , G06F9/3851 , G06F9/3867 , G06F9/48 , G06F11/00 , G06F11/1048 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F12/1009 , G06F17/16 , H03H17/0664 , G06F9/30018 , G06F9/325 , G06F9/381 , G06F9/3822 , G06F11/10 , G06F15/781 , G06F15/7807 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/68
摘要： A method is provided that includes performing, by a processor in response to a dual issue multiply instruction, multiplication of operands of the dual issue multiply instruction using multiplication units comprised in a data path of the processor and configured to operate together to determine a product of the operands, and storing, by the processor, the product in a storage location indicated by the dual issue multiply instruction.
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公开(公告)号：US11550575B2
公开(公告)日：2023-01-10
申请号：US17387260
申请日：2021-07-28
摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.
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公开(公告)号：US11237831B2
公开(公告)日：2022-02-01
申请号：US16878611
申请日：2020-05-20
IPC分类号： G06F9/30 , G06F17/16 , G06F9/38 , G06F7/487 , G06F7/499 , G06F7/24 , H03H17/06 , G06F7/53 , G06F9/48 , G06F7/57
摘要： A method is provided that includes receiving, in a permute network, a plurality of data elements for a vector instruction from a streaming engine, and mapping, by the permute network, the plurality of data elements to vector locations for execution of the vector instruction by a vector functional unit in a vector data path of a processor.
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公开(公告)号：US20210349832A1
公开(公告)日：2021-11-11
申请号：US17384858
申请日：2021-07-26
发明人： Timothy David Anderson , Mujibur Rahman , Dheera Balasubramanian Samudrala , Peter Richard Dent , Duc Quang Bui
IPC分类号： G06F12/1045 , G06F9/30 , G06F9/345 , G06F9/38 , G06F11/00 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F12/0862 , G06F12/1009
摘要： A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.
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公开(公告)号：US20200372099A1
公开(公告)日：2020-11-26
申请号：US16589133
申请日：2019-09-30
摘要： A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.
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公开(公告)号：US20200372098A1
公开(公告)日：2020-11-26
申请号：US16589126
申请日：2019-09-30
摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.
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公开(公告)号：US20200371808A1
公开(公告)日：2020-11-26
申请号：US16881327
申请日：2020-05-22
摘要： An integrated circuit, comprising an instruction pipeline that includes instruction fetch phase circuitry, instruction decode phase circuitry, and instruction execution circuitry. The instruction execution circuitry includes transformation circuitry for receiving an interleaved dual vector operand as an input and for outputting a first natural order vector including a first set of data values from the interleaved dual vector operand and a second natural order vector including a second set of data values from the interleaved dual vector operand.
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