公开(公告)号：US11996843B2

公开(公告)日：2024-05-28

申请号：US17567711

申请日：2022-01-03

Applicant: Texas Instruments Incorporated

Inventor： Timothy Paul Duryea

IPC: H03K19/23 ,  G01R31/317 ,  H03H7/06 ,  H03K3/037

CPC classification number: H03K19/23 ,  G01R31/31712 ,  H03H7/06 ,  H03K3/037

Abstract: Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.

公开(公告)号：US20230216505A1

公开(公告)日：2023-07-06

申请号：US17567711

申请日：2022-01-03

Applicant: Texas Instruments Incorporated

Inventor： Timothy Paul Duryea

IPC: H03K19/23 ,  H03H7/06 ,  H03K3/037 ,  G01R31/317

CPC classification number: H03K19/23 ,  H03H7/06 ,  H03K3/037 ,  G01R31/31712

Abstract: Described embodiments include a test system having first, second and third circuits having the same design and configured to receive a same input signal. A majority voter circuit has a first voter input coupled to a first circuit output, a second voter input coupled to a second circuit output, a third voter input coupled to a third circuit output, and a voter output. The output signal is equal to a signal present at least two of the voter inputs. A discrepancy detector circuit has first, second and third discrepancy inputs coupled to the first, second and third circuit outputs, respectively. A discrepancy output is configured to: provide a first logic signal responsive to the first, second and third circuit outputs having equal values; and provide a second logic signal responsive to the first, second and third circuit outputs having unequal values.

公开(公告)号：US10520971B2

公开(公告)日：2019-12-31

申请号：US15832071

申请日：2017-12-05

Applicant: Texas Instruments Incorporated

Inventor： Sri Navaneethakrishnan Easwaran ,  Vijayalakshmi Devarajan ,  Timothy Paul Duryea ,  Shanmuganand Chellamuthu

IPC: G05F3/26 ,  B60T8/172 ,  B60T8/1761 ,  H03K17/687

Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.