公开(公告)号：US20150019836A1

公开(公告)日：2015-01-15

申请号：US14327066

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mel Alan Phipps ,  Todd T. Hahn ,  Joseph Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/3012

Abstract: The number of registers required is reduced by overlapping scalar and vector registers. This also allows increased compiler flexibility when mixing scalar and vector instructions. Local register read ports are minimized by restricting read access. Dedicated predicate registers reduces requirements for general registers, and allows reduction of critical timing paths by allowing the predicate registers to be placed next to the predicate unit.

Abstract translation: 所需的寄存器数量通过重叠标量和向量寄存器来减少。 这也允许在混合标量和向量指令时增加编译器的灵活性。 通过限制读取访问来使本地寄存器读取端口最小化。 专用谓词寄存器减少通用寄存器的要求，并允许通过允许将谓词寄存器放置在谓词单元旁边来减少关键定时路径。

公开(公告)号：US20240086193A1

公开(公告)日：2024-03-14

申请号：US18507222

申请日：2023-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F9/3013

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

公开(公告)号：US11055095B2

公开(公告)日：2021-07-06

申请号：US16422823

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F9/30

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

公开(公告)号：US10732945B1

公开(公告)日：2020-08-04

申请号：US16422845

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F8/41 ,  G06F5/06 ,  G06F9/30

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

公开(公告)号：US09239735B2

公开(公告)日：2016-01-19

申请号：US14334352

申请日：2014-07-17

Applicant: Texas Instruments Incorporated

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Q. Bui ,  Mel A. Phipps ,  Todd T. Hahn

IPC: G06F9/45 ,  G06F9/48 ,  G06F9/44 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F8/30 ,  G06F8/443 ,  G06F8/4442 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3842

Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract translation: 在需要数据之前，静态调度处理器编译器会在程序中调度一个推测性负载。 在程序行为由于推测负载而变化之前，编译器会插入一条条件指令来确认或不肯定推测负载。 该条件不仅仅基于推测负载地址是否正确，而且还包括根据原始源代码的依赖性。 编译器可以与正交条件并行地静态安排两个或更多个分支。

公开(公告)号：US20150026444A1

公开(公告)日：2015-01-22

申请号：US14334352

申请日：2014-07-17

Applicant: Texas Instruments Incorporated

Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Duc Q. Bui ,  Mel A. Phipps ,  Todd T. Hahn

IPC: G06F9/30 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F8/30 ,  G06F8/443 ,  G06F8/4442 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3842

Abstract: A statically scheduled processor compiler schedules a speculative load in the program before the data is needed. The compiler inserts a conditional instruction confirming or disaffirming the speculative load before the program behavior changes due to the speculative load. The condition is not based solely upon whether the speculative load address is correct but preferably includes dependence according to the original source code. The compiler may statically schedule two or more branches in parallel with orthogonal conditions.

Abstract translation: 在需要数据之前，静态调度处理器编译器会在程序中调度一个推测性负载。 在程序行为由于推测负载而变化之前，编译器会插入一条条件指令来确认或不肯定推测负载。 该条件不仅仅基于推测负载地址是否正确，而且还包括根据原始源代码的依赖性。 编译器可以与正交条件并行地静态安排两个或更多个分支。