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    DYNAMIC SECURITY PROTECTION IN CONFIGURABLE ANALOG SIGNAL CHAINS
    11.
    发明公开
    DYNAMIC SECURITY PROTECTION IN CONFIGURABLE ANALOG SIGNAL CHAINS 审中-公开

    公开(公告)号：US20230204666A1

    公开(公告)日：2023-06-29

    申请号：US18175730

    申请日：2023-02-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Christy Leigh She

    IPC: G01R31/3185 ,  G06F21/45 ,  G06F21/31 ,  H04L9/40

    CPC classification number: G01R31/318536 ,  G06F21/45 ,  G06F21/31 ,  H04L63/1433

    Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.

    Hardware control path redundancy for functional safety of peripherals
    12.
    发明授权
    Hardware control path redundancy for functional safety of peripherals 有权

    公开(公告)号：US11604709B2

    公开(公告)日：2023-03-14

    申请号：US17409029

    申请日：2021-08-23

    Applicant: Texas Instruments Incorporated

    Inventor： Veeramanikandan Raju ,  Anand Kumar G

    IPC: G06F11/00 ,  G06F11/16 ,  G06F11/14 ,  G06F13/20 ,  G06F11/07

    Abstract: Techniques including receiving a first control value, starting a timeout counter based on receiving the first control value, receiving a second control value, determining whether the second control value is received before the timeout counter expires, and based on the determination that the second control value is received before the timeout counter expires: determining whether the first control value is the same as the second control value, and loading the first control value into a set of control registers based on the determination that the first control value is the same as the second control value.

    Method and system for file storage and access
    13.
    发明授权
    Method and system for file storage and access 有权

    公开(公告)号：US09817837B2

    公开(公告)日：2017-11-14

    申请号：US15413048

    申请日：2017-01-23

    Applicant: Texas Instruments Incorporated

    Inventor： Madan Srinivas ,  Veeramanikandan Raju ,  Keshava Munegowda

    IPC: G06F17/30

    CPC classification number: G06F17/30109 ,  G06F17/30091 ,  G06F17/30094 ,  G06F17/30203

    Abstract: Disclosed embodiments relate to storing and accessing files. In an embodiment, a method includes writing a file to a writing a file to a storage device having a file system having a file allocation table (FAT). Writing the file includes allocating a plurality of clusters of the file system to the file, wherein at least a portion of the allocated clusters is contiguous. The FAT includes a plurality of cluster addresses corresponding to the allocated clusters. A signature value is stored in a cluster address corresponding to a first cluster of the contiguous clusters to indicate the presence of the contiguous clusters. In each of a set of consecutive cluster addresses succeeding the cluster address corresponding to the first cluster, a value that partially represents the number of the contiguous clusters is stored. The number of contiguous clusters is determinable by combining the values stored in the consecutive cluster addresses.

    Communication system with mixed threshold voltage transistors
    14.
    发明授权
    Communication system with mixed threshold voltage transistors 有权

    公开(公告)号：US12266422B2

    公开(公告)日：2025-04-01

    申请号：US18610993

    申请日：2024-03-20

    Applicant: Texas Instruments Incorporated

    Inventor： Veeramanikandan Raju ,  Anand Kumar G

    IPC: G11C7/10 ,  G11C5/14 ,  G11C7/22

    Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.

    DISPARITIES BETWEEN VIEWS OF A STEREOSCOPIC IMAGE
    15.
    发明申请
    DISPARITIES BETWEEN VIEWS OF A STEREOSCOPIC IMAGE 有权

    公开(公告)号：US20250071308A1

    公开(公告)日：2025-02-27

    申请号：US18941906

    申请日：2024-11-08

    Applicant: Texas Instruments Incorporated

    Inventor： Veeramanikandan Raju ,  Wei Hong ,  Minhua Zhou

    IPC: H04N19/46 ,  H04N13/128 ,  H04N19/597 ,  H04N19/70

    Abstract: From a bit stream, at least the following are decoded: a stereoscopic image of first and second views; a maximum positive disparity between the first and second views; and a minimum negative disparity between the first and second views. In response to the maximum positive disparity violating a limit on positive disparity, a convergence plane of the stereoscopic image is adjusted to comply with the limit on positive disparity. In response to the minimum negative disparity violating a limit on negative disparity, the convergence plane is adjusted to comply with the limit on negative disparity.

    Hardware control path redundancy for functional safety of peripherals
    18.
    发明授权
    Hardware control path redundancy for functional safety of peripherals 有权

    公开(公告)号：US12072776B2

    公开(公告)日：2024-08-27

    申请号：US18166787

    申请日：2023-02-09

    Applicant: Texas Instruments Incorporated

    Inventor： Veeramanikandan Raju ,  Anand Kumar G

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F11/16 ,  G06F13/20

    CPC classification number: G06F11/1616 ,  G06F11/0745 ,  G06F11/0757 ,  G06F11/1441 ,  G06F13/20 ,  G06F2201/805

    Abstract: A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.

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