-
公开(公告)号：US12184297B2
公开(公告)日：2024-12-31
申请号：US18159305
申请日：2023-01-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Veeramanikandan Raju , Anand Kumar G
IPC: H03M1/06
Abstract: A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.
-
公开(公告)号：US12013436B2
公开(公告)日：2024-06-18
申请号：US18175730
申请日：2023-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Veeramanikandan Raju , Anand Kumar G , Christy Leigh She
IPC: G01R31/3185 , G06F21/31 , G06F21/45 , H04L9/40
CPC classification number: G01R31/318536 , G06F21/31 , G06F21/45 , H04L63/1433
Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.
-
公开(公告)号：US20230317123A1
公开(公告)日：2023-10-05
申请号：US17710879
申请日：2022-03-31
Applicant: Texas Instruments Incorporated
Inventor： Veeramanikandan Raju , Anand Kumar G
CPC classification number: G11C7/109 , G11C7/1063 , G11C7/222 , G11C7/1039 , G11C5/14
Abstract: A communications circuit with an input port, a switching circuit coupled to the input port, and a first and second memory coupled to the switching circuit. The communications circuit also includes controlling circuitry adapted to operate the switching circuit to couple data received at the input port to the first memory while the second memory is disabled from power and to couple data received at the input port to the second memory once the first memory is filled with valid data.
-
公开(公告)号：US11715188B1
公开(公告)日：2023-08-01
申请号：US17682735
申请日：2022-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Veeramanikandan Raju , Niraj Nandan , Samuel Paul Visalli , Jason A. T. Jones , Kedar Satish Chitnis , Gregory Raymond Shurtz , Prithvi Shankar Yeyyadi Anantha , Sriramakrishnan Govindarajan
CPC classification number: G06T7/0002 , G05B23/0259 , G06T1/20 , G06T3/40 , G06T7/97 , G06T2207/10016 , H04N17/00
Abstract: An electronic device may be configured to detect a fault in imaging and vision hardware accelerators. The electronic device may include a controller configured to select a first golden input frame of multiple golden input frames to perform a first self-test, and retrieve a first reference image signature corresponding to the first golden input frame. The electronic device may include a hardware accelerator module configured to obtain the first golden input frame, and generate a first output frame based on the first golden input frame. The electronic device may include a signature generator configured to generate a first generated image signature based on the first output frame. The electronic device may include a signature comparison module configured to compare the first generated image signature to the first reference image signature in order to determine whether the hardware accelerator module includes a fault at a first time.
-
公开(公告)号：US20220377362A1
公开(公告)日：2022-11-24
申请号：US17880512
申请日：2022-08-03
Applicant: Texas Instruments Incorporated
Inventor： Veeramanikandan Raju , Wei Hong , Minhua Zhou
IPC: H04N19/46 , H04N19/70 , H04N19/597 , H04N13/128
Abstract: From a bit stream, at least the following are decoded: a stereoscopic image of first and second views; a maximum positive disparity between the first and second views; and a minimum negative disparity between the first and second views. In response to the maximum positive disparity violating a limit on positive disparity, a convergence plane of the stereoscopic image is adjusted to comply with the limit on positive disparity. In response to the minimum negative disparity violating a limit on negative disparity, the convergence plane is adjusted to comply with the limit on negative disparity.
-
Patent Agency Ranking
公开(公告)号：US09432654B2
公开(公告)日：2016-08-30
申请号：US13669017
申请日：2012-11-05
Applicant: Texas Instruments Incorporated
Inventor： Veeramanikandan Raju , Gregory Hewes
CPC classification number: H04N13/133 , H04N13/128 , H04N13/144
Abstract: The present invention is drawn to a device for use with first stereoscopic data, second stereoscopic data and a display device. The device includes an input portion, a convergence data detecting portion, a convergence plane portion, a comparing portion and a modification portion. The input portion can receive the first stereoscopic data and the second stereoscopic data. The convergence data detecting portion can detect first convergence data within the first stereoscopic data and can detect second convergence data within the second stereoscopic data. The convergence plane portion can determine a first convergence plane based on the first convergence data and can determine a second convergence plane based on the second convergence data. The comparing portion can compare the first, convergence plane and the second convergence plane and can generate a convergence plane comparison. The modification portion can modify the first convergence data based on the convergence plane comparison.
Abstract translation: 本发明涉及一种用于第一立体数据，第二立体数据和显示装置的装置。 该装置包括输入部分，会聚数据检测部分，会聚平面部分，比较部分和修改部分。 输入部分可以接收第一立体数据和第二立体数据。 会聚数据检测部分可以检测第一立体数据内的第一会聚数据，并且可以检测第二立体数据内的第二会聚数据。 会聚平面部分可以基于第一会聚数据确定第一会聚平面，并且可以基于第二会聚数据确定第二会聚平面。 比较部分可以比较第一个会聚平面和第二个会聚平面，并可以产生一个会聚平面比较。 修改部分可以基于会聚平面比较来修改第一收敛数据。
-
公开(公告)号：US20160119660A1
公开(公告)日：2016-04-28
申请号：US14525197
申请日：2014-10-27
Applicant: Texas Instruments Incorporated
Inventor： Veeramanikandan Raju , Madhukar Budagavi
IPC: H04N21/2347
CPC classification number: H04N21/23476 , H04N21/8456
Abstract: A method for encrypting a video stream in a video encoder is provided that includes receiving the video stream and encrypting randomly selected pictures in the video stream as the video stream is encoded.
Abstract translation: 提供一种用于对视频编码器中的视频流进行加密的方法，该方法包括当视频流被编码时，接收视频流并对视频流中随机选择的图像进行加密。
-
公开(公告)号：US20250155327A1
公开(公告)日：2025-05-15
申请号：US18508889
申请日：2023-11-14
Applicant: Texas Instruments Incorporated
Inventor： Anand Kumar G , Veeramanikandan Raju
IPC: G01M99/00
Abstract: An example apparatus includes: interface circuitry; and diagnostic circuitry configured to: determine a set of signal chains that may be used by an application, a signal chain in the set to include an ordered sequence of one or more circuit modules; identify a first signal chain from the set that was used by the application; and run, in response to a determination that the circuit modules in the first signal chain are idle, a diagnostic test on the first signal chain.
-
公开(公告)号：US20250111096A1
公开(公告)日：2025-04-03
申请号：US18375732
申请日：2023-10-02
Applicant: Texas Instruments Incorporated
Inventor： Veeramanikandan Raju , Anand Kumar G
IPC: G06F21/75
Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to protect against voltage glitch attacks in microcontrollers. An example apparatus includes logic circuitry operable to, in response to a voltage glitch, pause processing circuitry; number generator circuitry operable to generate a number; a counter operable to, after the voltage glitch ends, adjust a count corresponding to the number; and the logic circuitry operable to unpause the processing circuitry after the count reaches a value.
-
公开(公告)号：US20240086681A1
公开(公告)日：2024-03-14
申请号：US18389336
申请日：2023-11-14
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Veeramanikandan Raju , Chaitanya Ghone , Deepak Poddar
CPC classification number: G06N3/04 , G06N3/045 , G06N3/088 , H04L63/0435 , H04L63/0464
Abstract: A CNN based-signal processing includes receiving of an encrypted output from a first layer of a multi-layer CNN data. The received encrypted output is subsequently decrypted to form a decrypted input to a second layer of the multi-layer CNN data. A convolution of the decrypted input with a corresponding decrypted weight may generate a second layer output, which may be encrypted and used as an encrypted input to a third layer of the multi-layer CNN data.
-
-
-
-
-
-
-
-
-
Search Results
63
records
(took 0.016 seconds)
