公开(公告)号：US20210258018A1

公开(公告)日：2021-08-19

申请号：US17307684

申请日：2021-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Chirag Chandrahas SHETTY ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M1/50 ,  H03M1/14 ,  H03M1/20 ,  H03M1/44

Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

公开(公告)号：US20200382128A1

公开(公告)日：2020-12-03

申请号：US16997975

申请日：2020-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Kumar Reddy NARU ,  Anand Jerry GEORGE ,  Shagun DUSAD ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/46

Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

公开(公告)号：US20190280703A1

公开(公告)日：2019-09-12

申请号：US16249225

申请日：2019-01-16

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy NARU ,  Narasimhan RAJAGOPAL ,  Shagun DUSAD ,  Viswanathan NAGARAJAN ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M1/06 ,  H03M1/00 ,  H03M1/04

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.