公开(公告)号：US20220209782A1

公开(公告)日：2022-06-30

申请号：US17133745

申请日：2020-12-24

Applicant: Texas Instruments Incorporated

Inventor： Narasimhan RAJAGOPAL ,  Chirag Chandrahas SHETTY ,  Neeraj SHRIVASTAVA ,  Prasanth K ,  Eeshan MIGLANI

IPC: H03M1/12 ,  H03L7/081 ,  H03K5/24

Abstract: A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.

公开(公告)号：US20220200620A1

公开(公告)日：2022-06-23

申请号：US17129180

申请日：2020-12-21

Applicant: Texas Instruments Incorporated

Inventor： Eeshan MIGLANI ,  Visvesvaraya Appala PENTAKOTA ,  Chirag Chandrahas SHETTY

IPC: H03M1/50 ,  H03M1/20 ,  H03M1/46

Abstract: A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.

公开(公告)号：US20210258018A1

公开(公告)日：2021-08-19

申请号：US17307684

申请日：2021-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Chirag Chandrahas SHETTY ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M1/50 ,  H03M1/14 ,  H03M1/20 ,  H03M1/44

Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

公开(公告)号：US20200259502A1

公开(公告)日：2020-08-13

申请号：US16860334

申请日：2020-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Chirag Chandrahas SHETTY ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M1/50 ,  H03M1/14 ,  H03M1/20 ,  H03M1/44

Abstract: An RF receiver including: an antenna cable of receiving an RF signal; a low noise amplifier coupled to the antenna and having an output; a bandpass filter coupled to the output of the low noise amplifier and having a voltage signal output, VIN; a conversion and folding circuit; and an analog-to-digital converter for converting the earlier-arriving or later-arriving delay signals into a digital code representing the voltage signal. The conversion and folding circuit having: a voltage-to-delay converter block, including preamplifiers, for converting the voltage signal into delay signals; and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals; and

公开(公告)号：US20200259501A1

公开(公告)日：2020-08-13

申请号：US16860145

申请日：2020-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Visvesvaraya Appala PENTAKOTA ,  Rishi SOUNDARARAJAN ,  Shagun DUSAD ,  Chirag Chandrahas SHETTY

IPC: H03M1/38 ,  H03K5/24

Abstract: An analog-to-digital converter, comprising: a voltage to delay circuit having a voltage input, a threshold voltage input, a first output and a second output, wherein a leading edge of the first output is delayed, by a first delay magnitude, in relationship to a leading edge of the second output; and a first stage including: a first logic gate having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, and an output; and a first stage delay comparator having a first input coupled to the first output of the voltage to delay circuit, a second input coupled to the second output of the voltage to delay circuit, a sign signal output and a first stage delay comparator output, wherein the sign signal output represents whether the voltage input is greater than or less than the threshold voltage input. The analog-to-digital converter further includes a digital block having an input connected to the sign signal output of the delay comparator.