公开(公告)号：US08698539B1

公开(公告)日：2014-04-15

申请号：US13739228

申请日：2013-01-11

Applicant: Texas Instruments Incorporated

Inventor： Jasbir Singh Nayyar ,  Sreenath Narayanan Potty ,  Mukesh Kumar ,  Vivek Singhal

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: A clock generation circuit in an IC is provided for mitigating signal interferences caused by an aggressor block operable on a first clock signal with a frequency range of a victim block. The clock generation circuit includes a gating circuit configured to perform gating of a second clock signal to generate a third clock signal based on control signal. An average frequency of the third clock signal is substantially matched to a frequency of the first clock signal, and harmonics of the third clock signal do not interfere with the frequency range of the victim block. The clock generation circuit further includes a FIFO buffer circuit configured to receive the first clock signal as a write clock and the third clock signal as read clock, and a control circuit for generating the control signal based on an occupancy level of FIFO buffer circuit and a plurality of random numbers.

Abstract translation: 提供了IC中的时钟发生电路，用于减轻由在受害者块的频率范围内的第一时钟信号上可操作的攻击者块引起的信号干扰。 时钟发生电路包括门控电路，其被配置为基于控制信号执行第二时钟信号的门控以产生第三时钟信号。 第三时钟信号的平均频率基本上与第一时钟信号的频率相匹配，并且第三时钟信号的谐波不会干扰受害者块的频率范围。 时钟生成电路还包括：FIFO缓冲电路，被配置为将第一时钟信号作为写时钟接收，第三时钟信号作为读时钟;以及控制电路，用于基于FIFO缓冲电路的占用电平和 多个随机数。

公开(公告)号：US09319045B1

公开(公告)日：2016-04-19

申请号：US14584511

申请日：2014-12-29

Applicant: Texas Instruments Incorporated

Inventor： Sudesh Chandra Srivastava ,  Vivek Singhal

IPC: H03K19/003 ,  H03K19/00

CPC classification number: H03K19/00361 ,  H03K19/0008

Abstract: A circuit for reducing gate leakage current in a switchable power domain of a CMOS (complementary metal oxide semiconductor) integrated circuit chip includes a first transistor having a drain electrode coupled to a first terminal of a power switch having a second terminal coupled to a first reference voltage, the first transistor having a gate electrode, a body electrode, and a source electrode. The source electrode and body electrodes are coupled to a second reference voltage. The first transistor has a relatively high first gate leakage current that flows from its gate electrode to its body electrode if the power switch is open and a voltage of the gate electrode of the first transistor representing a first logic level exceeds a voltage of the body electrode by more than a first predetermined amount. A first circuit produces a relatively low voltage on the gate electrode of the first transistor representing a second logic level to substantially reduce the first gate leakage current when reduced power consumption of the chip is needed.

Abstract translation: 一种用于减小CMOS（互补金属氧化物半导体）集成电路芯片的可切换电源域中的栅极漏电流的电路包括：第一晶体管，具有耦合到功率开关的第一端的漏电极，第一端与第一参考 电压，第一晶体管具有栅电极，体电极和源电极。 源电极和主体电极耦合到第二参考电压。 第一晶体管具有相对较高的第一栅极泄漏电流，如果电源开关断开并且第一晶体管的栅电极的电压超过体电极的电压，则从其栅电极流到其主体电极 超过第一预定量。 第一电路在第一晶体管的栅电极上产生代表第二逻辑电平的相对较低的电压，以在需要降低芯片的功耗时大幅降低第一栅极漏电流。

公开(公告)号：US08981821B2

公开(公告)日：2015-03-17

申请号：US13739256

申请日：2013-01-11

Applicant: Texas Instruments Incorporated

Inventor： Sreenath Narayanan Potty ,  Jasbir Singh Nayyar ,  Vivek Singhal

IPC: H03B19/00 ,  G06F1/04

CPC classification number: G06F1/04 ,  H04B15/04

Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.

Abstract translation: 公开了几种方法和电路，其被配置为减轻可操作在IC中的至少一个受害电路的干扰频率范围内的第一时钟信号上的至少一个侵扰电路的信号干扰。 在一个实施例中，信号干扰减轻电路被配置为与侵扰电路相关联并且包括时钟分频器电路和控制电路。 时钟分频器电路被配置为基于第二时钟信号和分频因子模式产生第一时钟信号。 控制电路与时钟分频器电路耦合，并配置为确定分频系数模式，并将分频系数模式提供给时钟分频器电路。 分割因子模式包括基于多个随机数随机选择的多个分频因子，并且被配置为控制与信号干扰减轻电路相关联的吞吐量频率。

公开(公告)号：US20140197875A1

公开(公告)日：2014-07-17

申请号：US13739256

申请日：2013-01-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenath Narayanan Potty ,  Jasbir Singh Nayyar ,  Vivek Singhal

IPC: G06G7/16

CPC classification number: G06F1/04 ,  H04B15/04

Abstract: Several methods and circuits configured to mitigate signal interference of at least one aggressor circuit operable on a first clock signal within an interfering frequency range of at least one victim circuit in an IC are disclosed. In an embodiment, a signal interference mitigation circuit is configured to be associated with the aggressor circuit and includes a clock divider circuit and a control circuit. The clock divider circuit is configured to generate the first clock signal based on a second clock signal and a division factor pattern. The control circuit is coupled with the clock divider circuit and configured to determine the division factor pattern and provide the division factor pattern to the clock divider circuit. The division factor pattern comprises a plurality of division factors selected randomly based on a plurality of random numbers, and is configured to control a throughput frequency associated with the signal interference mitigation circuit.

Abstract translation: 公开了几种方法和电路，其被配置为减轻可操作在IC中的至少一个受害电路的干扰频率范围内的第一时钟信号上的至少一个侵扰电路的信号干扰。 在一个实施例中，信号干扰减轻电路被配置为与侵扰电路相关联并且包括时钟分频器电路和控制电路。 时钟分频器电路被配置为基于第二时钟信号和分频因子模式产生第一时钟信号。 控制电路与时钟分频器电路耦合，并配置为确定分频系数模式，并将分频系数模式提供给时钟分频器电路。 分割因子模式包括基于多个随机数随机选择的多个分频因子，并且被配置为控制与信号干扰减轻电路相关联的吞吐量频率。