公开(公告)号：US20160191066A1

公开(公告)日：2016-06-30

申请号：US14584550

申请日：2014-12-29

Applicant: Texas Instruments Incorporated

Inventor： Sreenath Narayanan Potty ,  Vivek Singhal ,  Sumanth Reddy Poddutur

IPC: H03L7/081 ,  H03K3/013

CPC classification number: H03L7/0818 ,  H03K3/013

Abstract: A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.

Abstract translation: 公开了一种提供数字噪声杂散消除的时钟抖动电路。 时钟抖动电路包括接收输入时钟的控制单元。 ICG（集成时钟门控）单元接收输入时钟并从控制单元接收使能信号。 ICG单元产生门控时钟。 粗略抖动单元接收门控时钟并从控制单元接收粗选信号。 粗抖动单元产生粗抖动时钟。 精细抖动单元接收粗略抖动时钟并从控制单元接收精细选择信号。 精细的抖动单元产生精细的抖动时钟。

公开(公告)号：US20170194949A1

公开(公告)日：2017-07-06

申请号：US14986444

申请日：2015-12-31

Applicant: Texas Instruments Incorporated

Inventor： Sudesh Chandra Srivastava ,  Vivek Singhal

IPC: H03K3/3562 ,  H01L27/02 ,  H01L29/10 ,  H01L27/088

CPC classification number: H03K3/3562 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/1095 ,  H03K3/35625

Abstract: An integrated circuit device having a p-well plane, a plurality of substantially parallel n-well rows, and a logic cell. The p-well plane is comprised of p-type semiconductor material. Each n-well row comprises an n-type layer disposed on the surface of the p-well plane. The plurality of n-well rows includes a first n-well row and a second n-well row. The logic cell is arranged on the p-well plane and the footprint of the logic cell encompasses both the first and second n-well rows.

公开(公告)号：US20160356849A1

公开(公告)日：2016-12-08

申请号：US15239279

申请日：2016-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenath Narayanan Potty ,  Rajesh Mittal ,  Mudasir Shafat Kawoosa ,  Vivek Singhal

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3183 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318563

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

Abstract translation: 实施例提供了一种用于测试集成电路的电路。 该电路包括输入转换器，其接收N个扫描输入并产生M个伪扫描输入，其中M和N是整数。 扫描压缩架构耦合到输入转换器并响应于M个伪扫描输入产生P个伪扫描输出。 输出转换器耦合到扫描压缩架构并响应于P伪扫描输出产生Q扫描输出，其中P和Q是整数。 输入转换器以第一频率接收N个扫描输入并以第二频率产生M个伪扫描输入，并且输出转换器以第二频率接收P个伪扫描输出，并以第一个频率产生Q个扫描输出。

公开(公告)号：US09419630B2

公开(公告)日：2016-08-16

申请号：US14584550

申请日：2014-12-29

Applicant: Texas Instruments Incorporated

Inventor： Sreenath Narayanan Potty ,  Vivek Singhal ,  Sumanth Reddy Poddutur

IPC: G06F1/04 ,  H03K3/00 ,  H03L7/081 ,  H03K3/013

CPC classification number: H03L7/0818 ,  H03K3/013

Abstract: A clock dithering circuit that provides cancellation of digital noise spurs is disclosed. The clock dithering circuit includes a control unit that receives an input clock. An ICG (integrated clock gating) cell receives the input clock and receives an enable signal from the control unit. The ICG cell generates a gated clock. A coarse dither unit receives the gated clock and receives a coarse select signal from the control unit. The coarse dither unit generates a coarse dither clock. A fine dither unit receives the coarse dither clock and receives a fine select signal from the control unit. The fine dither unit generates a fine dither clock.

Abstract translation: 公开了一种提供数字噪声杂散消除的时钟抖动电路。 时钟抖动电路包括接收输入时钟的控制单元。 ICG（集成时钟门控）单元接收输入时钟并从控制单元接收使能信号。 ICG单元产生门控时钟。 粗略抖动单元接收门控时钟并从控制单元接收粗选信号。 粗抖动单元产生粗抖动时钟。 精细抖动单元接收粗略抖动时钟并从控制单元接收精细选择信号。 精细的抖动单元产生精细的抖动时钟。

公开(公告)号：US09705481B1

公开(公告)日：2017-07-11

申请号：US14986444

申请日：2015-12-31

Applicant: Texas Instruments Incorporated

Inventor： Sudesh Chandra Srivastava ,  Vivek Singhal

IPC: H03K3/35 ,  H03K3/3562 ,  H01L27/088 ,  H01L27/02 ,  H01L29/10

CPC classification number: H03K3/3562 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/1095 ,  H03K3/35625

Abstract: An integrated circuit device having a p-well plane, a plurality of substantially parallel n-well rows, and a logic cell. The p-well plane is comprised of p-type semiconductor material. Each n-well row comprises an n-type layer disposed on the surface of the p-well plane. The plurality of n-well rows includes a first n-well row and a second n-well row. The logic cell is arranged on the p-well plane and the footprint of the logic cell encompasses both the first and second n-well rows.

公开(公告)号：US20160266202A1

公开(公告)日：2016-09-15

申请号：US14985699

申请日：2015-12-31

Applicant: Texas Instruments Incorporated

Inventor： Rajesh Kumar Mittal ,  Wilson Pradeep ,  Vivek Singhal

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31725 ,  G01R31/318538 ,  G01R31/318563 ,  G01R31/318575

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.

Abstract translation: 扫描链可以形成在整个集成电路中，其中扫描链包括至少第一段和第二段。 通过以奇数时钟对第一段中的多个扫描单元的其余部分进行计时，同时以奇数时钟计时第一段的第一扫描单元，将测试图案的第一部分扫描到第一段中，其中奇数 时钟与偶数时钟异相，其中偶数时钟和奇数时钟具有等于测试图案的扫描速率除以整数N的速率。测试图案的第二部分被扫描到第二段中 以奇数时钟对第二段中的多个扫描单元进行计时，使得测试图案的第二部分不被扫描到第一段中。

公开(公告)号：US20150323596A1

公开(公告)日：2015-11-12

申请号：US14272760

申请日：2014-05-08

Applicant: Texas Instruments Incorporated

Inventor： Sreenath Narayanan Potty ,  Rajesh Mittal ,  Mudasir Shafat Kawoosa ,  Vivek Singhal

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3183 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318563

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

Abstract translation: 实施例提供了一种用于测试集成电路的电路。 该电路包括输入转换器，其接收N个扫描输入并产生M个伪扫描输入，其中M和N是整数。 扫描压缩架构耦合到输入转换器并响应于M个伪扫描输入产生P个伪扫描输出。 输出转换器耦合到扫描压缩架构并响应于P伪扫描输出产生Q扫描输出，其中P和Q是整数。 输入转换器以第一频率接收N个扫描输入并以第二频率产生M个伪扫描输入，并且输出转换器以第二频率接收P个伪扫描输出，并以第一个频率产生Q个扫描输出。

公开(公告)号：US09970987B2

公开(公告)日：2018-05-15

申请号：US15239279

申请日：2016-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreenath Narayanan Potty ,  Rajesh Mittal ,  Mudasir Shafat Kawoosa ,  Vivek Singhal

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3183 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318563

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

公开(公告)号：US09535123B2

公开(公告)日：2017-01-03

申请号：US14985699

申请日：2015-12-31

Applicant: Texas Instruments Incorporated

Inventor： Rajesh Kumar Mittal ,  Wilson Pradeep ,  Vivek Singhal

IPC: G01R31/3177 ,  G01R31/28 ,  G01R31/317 ,  G01R31/44

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31725 ,  G01R31/318538 ,  G01R31/318563 ,  G01R31/318575

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.

Abstract translation: 扫描链可以形成在整个集成电路中，其中扫描链包括至少第一段和第二段。 通过以奇数时钟对第一段中的多个扫描单元的其余部分进行计时，同时以奇数时钟计时第一段的第一扫描单元，将测试图案的第一部分扫描到第一段中，其中奇数 时钟与偶数时钟异相，其中偶数时钟和奇数时钟具有等于测试图案的扫描速率除以整数N的速率。测试图案的第二部分被扫描到第二段中 以奇数时钟对第二段中的多个扫描单元进行计时，使得测试图案的第二部分不被扫描到第一段中。

公开(公告)号：US09448284B2

公开(公告)日：2016-09-20

申请号：US14272760

申请日：2014-05-08

Applicant: Texas Instruments Incorporated

Inventor： Sreenath Narayanan Potty ,  Rajesh Mittal ,  Mudasir Shafat Kawoosa ,  Vivek Singhal

IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3183 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318563

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

Abstract translation: 实施例提供了一种用于测试集成电路的电路。 该电路包括输入转换器，其接收N个扫描输入并产生M个伪扫描输入，其中M和N是整数。 扫描压缩架构耦合到输入转换器并响应于M个伪扫描输入产生P个伪扫描输出。 输出转换器耦合到扫描压缩架构并响应于P伪扫描输出产生Q扫描输出，其中P和Q是整数。 输入转换器以第一频率接收N个扫描输入并以第二频率产生M个伪扫描输入，并且输出转换器以第二频率接收P个伪扫描输出，并以第一个频率产生Q个扫描输出。