中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.016 seconds)

    Memory optimized GNSS correlator
    2.
    发明授权
    Memory optimized GNSS correlator 有权

    公开(公告)号：US11598883B2

    公开(公告)日：2023-03-07

    申请号：US17028729

    申请日：2020-09-22

    Applicant: Texas Instruments Incorporated

    Inventor： Jasbir Singh Nayyar ,  Sreenath Narayanan Potty ,  Sunil Chomal

    IPC: G01S19/30 ,  H04B1/7075

    Abstract: A personal navigation device includes a correlator for processing GNSS signals from a constellation of satellites A signal is received from a navigation beacon containing a repeating code word, in which the code word includes a number N of samples corresponding to N phases, and in which reception of each code word occurs within a defined time period T. The sequence of N code samples is correlated with a known code word to determine a maximum value of correlation for a particular phase of the received signal. The correlation is performed using a correlator of size M, in which M is less than N, such that N/M=P complete correlations for a partial code phase are performed such that each correlation of a partial code phase is performed within a time period of approximately T/P. All P correlations of partial code phases are completed within time T.

    Timing for IC chip
    4.
    发明授权
    Timing for IC chip 有权

    公开(公告)号：US10142095B2

    公开(公告)日：2018-11-27

    申请号：US15334979

    申请日：2016-10-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jasbir Singh Nayyar ,  Brian Ginsburg ,  Karthik Subburaj

    IPC: H04L7/00 ,  H01Q1/22

    Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.

    MULTIPLE CHIRP GENERATION IN A RADAR SYSTEM
    5.
    发明申请
    MULTIPLE CHIRP GENERATION IN A RADAR SYSTEM 有权

    公开(公告)号：US20220137182A1

    公开(公告)日：2022-05-05

    申请号：US17574680

    申请日：2022-01-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Tom Altus ,  Jasbir Singh Nayyar ,  Karthik Ramasubramanian ,  Brian Paul Ginsburg

    IPC: G01S7/35 ,  G01S13/34

    Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

    Memory optimized GNSS correlator
    6.
    发明授权
    Memory optimized GNSS correlator 有权

    公开(公告)号：US10816673B2

    公开(公告)日：2020-10-27

    申请号：US14919710

    申请日：2015-10-21

    Applicant: Texas Instruments Incorporated

    Inventor： Jasbir Singh Nayyar ,  Sreenath Narayanan Potty ,  Sunil Chomal

    IPC: G01S19/30 ,  H04B1/7075

    Abstract: A personal navigation device includes a correlator for processing GNSS signals from a constellation of satellites A signal is received from a navigation beacon containing a repeating code word, in which the code word includes a number N of samples corresponding to N phases, and in which reception of each code word occurs within a defined time period T. The sequence of N code samples is correlated with a known code word to determine a maximum value of correlation for a particular phase of the received signal. The correlation is performed using a correlator of size M, in which M is less than N, such that N/M=P complete correlations for a partial code phase are performed such that each correlation of a partial code phase is performed within a time period of approximately T/P. All P correlations of partial code phases are completed within time T.

    Buffer Sample Size Control for Variable Chirp Radar
    7.
    发明申请
    Buffer Sample Size Control for Variable Chirp Radar 审中-公开

    公开(公告)号：US20190219671A1

    公开(公告)日：2019-07-18

    申请号：US16359544

    申请日：2019-03-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jasbir Singh Nayyar ,  Brian Ginsburg

    IPC: G01S7/35 ,  G01S13/34 ,  G01S7/285 ,  G01S13/28 ,  G01S13/93

    CPC classification number: G01S7/352 ,  G01S7/285 ,  G01S13/282 ,  G01S13/343 ,  G01S13/931

    Abstract: A method of radar signal processing includes providing an analog front end (AFE) including an amplifier coupled between an antenna and an ADC in a receive path, where an ADC output is coupled to an input of an elastic ADC buffer (elastic buffer) including a divided memory with for writing samples from the ADC (samples) while reading earlier written samples to a first signal processor by a high speed interface. A transmit path includes at least one power amplifier provided by the AFE coupled to drive an antenna. A Greatest Common Divisor (GCD) is determined across all chirps in a radar frame programmed to be used. For each frame a sample size for the elastic buffer is dynamically controlled constant to be equal to the GCD for reading samples from one memory block and writing samples to another memory block throughout all chirps in the frame.

    Distributed Radar Signal Processing in a Radar System
    9.
    发明申请
    Distributed Radar Signal Processing in a Radar System 审中-公开
    雷达系统中的分布式雷达信号处理

    公开(公告)号：US20160018511A1

    公开(公告)日：2016-01-21

    申请号：US14633647

    申请日：2015-02-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jasbir Singh Nayyar ,  Brian Paul Ginsburg ,  Sudipto Bose ,  Murtaza Ali

    IPC: G01S7/03 ,  G01S13/42 ,  G01S13/87 ,  G01S7/35 ,  G01S13/04

    CPC classification number: G01S7/03 ,  G01S7/352 ,  G01S13/343 ,  G01S13/42 ,  G01S13/87 ,  G01S13/878 ,  G01S13/931 ,  G01S2007/356

    Abstract: A cascaded radar system is provided that includes a first radar system-on-a-chip (SOC) operable to perform an initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels of the radar SOC, a second radar SOC operable to perform the initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels in the radar SOC, and a processing unit coupled to the first radar SOC and the second radar SOC to receive results of the initial portion of signal processing from each radar SOC, the processing unit operable to perform a remaining portion of the signal processing for object detection using these results.

    Abstract translation: 提供了一种级联雷达系统，其包括第一雷达系统芯片（SOC），其可操作以执行信号处理的初始部分，用于由雷达SOC的多个接收通道产生的数字差拍信号上的物体检测;第二雷达 SOC，用于对由雷达SOC中的多个接收信道产生的数字差拍信号执行对象检测的信号处理的初始部分，以及耦合到第一雷达SOC和第二雷达SOC的处理单元，以接收初始部分的结果 来自每个雷达SOC的信号处理，处理单元可操作以使用这些结果执行用于对象检测的信号处理的剩余部分。

    Multiple chirp generation in a radar system
    10.
    发明授权
    Multiple chirp generation in a radar system 有权

    公开(公告)号：US11927690B2

    公开(公告)日：2024-03-12

    申请号：US17574680

    申请日：2022-01-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Tom Altus ,  Jasbir Singh Nayyar ,  Karthik Ramasubramanian ,  Brian Paul Ginsburg

    IPC: G01S7/35 ,  G01S13/34

    CPC classification number: G01S7/35 ,  G01S13/34 ,  G01S13/343

    Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

Patent Agency Ranking