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    ULTRA-LOW POWER COMPARATOR WITH SAMPLING CONTROL LOOP ADJUSTING FREQUENCY AND/OR SAMPLE APERTURE WINDOW
    12.
    发明申请
    ULTRA-LOW POWER COMPARATOR WITH SAMPLING CONTROL LOOP ADJUSTING FREQUENCY AND/OR SAMPLE APERTURE WINDOW 有权
    具有采样控制环调节频率和/或采样孔径的超低功耗比较器

    公开(公告)号：US20170077912A1

    公开(公告)日：2017-03-16

    申请号：US14852155

    申请日：2015-09-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Wei Fu ,  Keith Edmund Kunz ,  Russell George Byrd

    IPC: H03K5/00 ,  G05F1/46

    CPC classification number: H03K5/00006 ,  G05F1/00 ,  G05F1/46 ,  H02M3/04 ,  H02M3/156 ,  H02M3/158 ,  H02M3/1588 ,  H02M2001/0006 ,  H02M2001/0032 ,  H02M2001/0048 ,  Y02B70/1491 ,  Y02B70/16

    Abstract: Methods and apparatus for minimizing average quiescent current for a desire voltage error in a comparator are disclosed. An example method includes receiving a first voltage and a reference voltage, outputting a second voltage when the first voltage is lower than the reference voltage, wherein the outputting of the second voltage increases the first voltage, counting a number of clock cycles while the first voltage is higher than the reference voltage, comparing the number of clock cycles to a maximum number of clock cycles and a minimum number of clock cycles, when the number of clock cycles is above the maximum number of clock cycles, decreasing a frequency of a clock associated with the number of clock cycles, and when the number of clock cycles is below the minimum number of clock cycles increase the frequency of the clock.

    Abstract translation: 公开了用于使比较器中的期望电压误差的平均静态电流最小化的方法和装置。 示例性方法包括接收第一电压和参考电压，当第一电压低于参考电压时输出第二电压，其中输出第二电压增加第一电压，对第一电压进行计数，同时第一电压 高于参考电压时，将时钟周期数与最大时钟周期数和最小时钟周期数进行比较，当时钟周期数高于最大时钟周期数时，减少时钟相关频率 具有时钟周期数，并且当时钟周期数低于最小时钟周期数时，会增加时钟频率。

    PHASE LOCK LOOP REFERENCE LOSS DETECTION
    14.
    发明申请
    PHASE LOCK LOOP REFERENCE LOSS DETECTION 有权

    公开(公告)号：US20220103181A1

    公开(公告)日：2022-03-31

    申请号：US17550123

    申请日：2021-12-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

    IPC: H03L7/087 ,  H03L7/099

    Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

    PHASE LOCK LOOP REFERENCE LOSS DETECTION
    15.
    发明申请
    PHASE LOCK LOOP REFERENCE LOSS DETECTION 审中-公开

    公开(公告)号：US20200127667A1

    公开(公告)日：2020-04-23

    申请号：US16167440

    申请日：2018-10-22

    Applicant: Texas Instruments Incorporated

    Inventor： Shailesh Ganapat Ghotgalkar ,  Wei Fu ,  Venkatseema Das

    IPC: H03L7/087 ,  H03L7/099

    Abstract: In described examples, a first clock generator generates an output clock signal in response to an input reference signal and in response to a feedback signal that is generated in response to the output clock signal. A code generator generates a code in response to the input reference signal. A loss detector generates an indication of a loss of the input reference signal in response to the feedback signal and at least two codes generated by the code generator.

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