公开(公告)号：US20150340081A1

公开(公告)日：2015-11-26

申请号：US14814798

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

Abstract translation: 用于对容易受到晶体管特性的晶体管特性偏移的晶体管的操作时间筛选互补金属氧化物半导体CMOS集成电路的方法，诸如包括CMOS静态随机存取存储器（SRAM）单元的集成电路。 对于由交叉耦合CMOS反相器形成的SRAM单元的示例，可以将单独的接地电压电平施加到驱动器晶体管的源节点，或者可以将单独的电源电压电平施加到负载晶体管的源节点（或两者 ）。 以这种方式施加到晶体管的不对称偏置电压将降低晶体管驱动电流，并且因此可以模拟偏置温度不稳定性（BTI）的影响。 因此可以识别易受阈值电压偏移的电池。

公开(公告)号：US20140078819A1

公开(公告)日：2014-03-20

申请号：US14083637

申请日：2013-11-19

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh ,  Anand Seshardi ,  Zhonghai Shi

IPC: G11C11/413

CPC classification number: G11C11/413 ,  G11C11/412 ,  H01L27/1104

Abstract: Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.

Abstract translation: 在具有不对称上下文（例如缓冲电路）的静态随机存取存储器（SRAM）单元中的平衡电性能。 每个存储单元包括诸如读缓冲器的电路特征，其具有比单元内的其它晶体管更大的晶体管尺寸和特征，并且其中特征不对称影响较小单元晶体管。 为了获得最佳性能，单元晶体管对将彼此电气匹配。 更接近不对称特征的单元晶体管中的一个或多个不同地构成，例如具有不同的沟道宽度，沟道长度或净沟道掺杂剂浓度，以补偿不对称特征的邻近效应。

公开(公告)号：US20130343136A1

公开(公告)日：2013-12-26

申请号：US14010881

申请日：2013-08-27

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/41 ,  G11C29/022

Abstract: An SRAM with buffered-read bit cells is disclosed (FIGS. 1-6). The integrated circuit includes a plurality of memory cells (102). Each memory cell has a plurality of transistors (200, 202). A first memory cell (FIG. 2) is arranged to store a data signal in response to an active write word line (WWL) and to produce the data signal in response to an active read word line (RWL). A test circuit (104) formed on the integrated circuit is operable to test current and voltage characteristics of each transistor of the plurality of transistors of the first memory cell (FIGS. 7-10).

Abstract translation: 公开了具有缓冲读位元的SRAM（图1-6）。 集成电路包括多个存储单元（102）。 每个存储单元具有多个晶体管（200,202）。 第一存储器单元（图2）被布置为响应于有效写入字线（WWL）存储数据信号，并且响应于有源读取字线（RWL）产生数据信号。 形成在集成电路上的测试电路（104）可操作以测试第一存储单元的多个晶体管中每个晶体管的电流和电压特性（图7-10）。

公开(公告)号：US09805788B2

公开(公告)日：2017-10-31

申请号：US14814750

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/417 ,  G11C29/00 ,  G11C11/419 ,  G11C29/08 ,  G11C29/50 ,  G11C11/41

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

公开(公告)号：US20150340084A1

公开(公告)日：2015-11-26

申请号：US14814785

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/419 ,  G11C29/00

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

公开(公告)号：US08716808B2

公开(公告)日：2014-05-06

申请号：US13861585

申请日：2013-04-12

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: H01L27/092

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207

Abstract: An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array.

Abstract translation: 一种集成电路，其包括在存储单元阵列内具有周期性深阱结构的互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）。 深阱结构与存储单元阵列中相同导电类型（例如，n型）的表面阱区域接触，形成存储单元阵列区域中的n型和p型半导体材料的二维栅格 。 偏置导体可以接触网格以施加期望的阱偏置电压，例如在与存储单元阵列相邻的连接区域或外围电路中。

公开(公告)号：US20130320458A1

公开(公告)日：2013-12-05

申请号：US13861585

申请日：2013-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207

Abstract: An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array.

Abstract translation: 一种集成电路，其包括在存储单元阵列内具有周期性深阱结构的互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）。 深阱结构与存储单元阵列中相同导电类型（例如，n型）的表面阱区域接触，形成存储单元阵列区域中的n型和p型半导体材料的二维栅格 。 偏置导体可以接触网格以施加期望的阱偏置电压，例如在与存储单元阵列相邻的连接区域或外围电路中。

公开(公告)号：US09466356B2

公开(公告)日：2016-10-11

申请号：US14814798

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/417 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C11/41

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.

公开(公告)号：US09208832B2

公开(公告)日：2015-12-08

申请号：US13723639

申请日：2012-12-21

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Yang Yi ,  Wah Kit Loh

IPC: G11C5/14 ,  G11C29/50 ,  G11C29/02 ,  G11C29/12 ,  G11C29/26 ,  G11C11/41 ,  G11C29/40 ,  G11C29/04

CPC classification number: G11C5/147 ,  G11C11/41 ,  G11C29/021 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/40 ,  G11C29/50004 ,  G11C2029/0401

Abstract: A method of testing large-scale integrated circuits including multiple instances of memory arrays, and an integrated circuit structure for assisting such testing. In one embodiment, voltage drops due to parasitic resistance in array bias conductors are determined by extracting layout parameters, and subsequent circuit simulation that derives the voltage drops in those conductors during operation of each memory array. In another embodiment, sense lines from each memory array are selectively connected to a test sense terminal of the integrated circuit, at which the array bias voltage at each memory array is externally measured. Feedback control of the applied voltage to arrive at the desired array bias voltage can be performed.

Abstract translation: 一种测试包括多个存储器阵列实例的大规模集成电路的方法，以及用于辅助这种测试的集成电路结构。 在一个实施例中，通过提取布局参数和随后的电路模拟来确定阵列偏置导体中的寄生电阻引起的电压降，其导出每个存储器阵列操作期间那些导体中的电压降。 在另一个实施例中，来自每个存储器阵列的感测线选择性地连接到集成电路的测试感测端子，在该测试检测端子处外部测量每个存储器阵列处的阵列偏置电压。 可以进行施加电压的反馈控制以达到期望的阵列偏置电压。

公开(公告)号：US20150348615A1

公开(公告)日：2015-12-03

申请号：US14814750

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Xiaowei Deng ,  Wah Kit Loh

IPC: G11C11/419 ,  G11C29/08

CPC classification number: G11C11/417 ,  G11C11/41 ,  G11C11/419 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  G11C2029/5002

Abstract: A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified.