公开(公告)号：US10297578B2

公开(公告)日：2019-05-21

申请号：US15706017

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20200343263A1

公开(公告)日：2020-10-29

申请号：US16927309

申请日：2020-07-13

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  H01L25/065 ,  H01L23/00

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20200295037A1

公开(公告)日：2020-09-17

申请号：US16564783

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun Iijima ,  Masayoshi Tagami ,  Shinya Arai ,  Takahiro Tomimatsu

IPC: H01L27/11582 ,  H01L23/00 ,  H01L23/522 ,  H01L27/11573

Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.

公开(公告)号：US10741527B2

公开(公告)日：2020-08-11

申请号：US16390639

申请日：2019-04-22

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.