公开(公告)号：US11063062B2

公开(公告)日：2021-07-13

申请号：US16564783

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun Iijima ,  Masayoshi Tagami ,  Shinya Arai ,  Takahiro Tomimatsu

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/00

Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.

公开(公告)号：US10553612B2

公开(公告)日：2020-02-04

申请号：US16460410

申请日：2019-07-02

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/00 ,  G11C16/26 ,  G11C16/04 ,  G11C5/02

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US10381374B2

公开(公告)日：2019-08-13

申请号：US15911369

申请日：2018-03-05

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US10748928B2

公开(公告)日：2020-08-18

申请号：US16707646

申请日：2019-12-09

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H01L27/11582 ,  H01L25/065 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/00 ,  G11C16/26 ,  G11C16/04 ,  G11C5/02

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US20200111810A1

公开(公告)日：2020-04-09

申请号：US16707646

申请日：2019-12-09

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L27/11582 ,  H01L23/00 ,  H01L25/065 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11565

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection

公开(公告)号：US10331028B2

公开(公告)日：2019-06-25

申请号：US15011915

申请日：2016-02-01

Applicant: Toshiba Memory Corporation

Inventor： Takahito Nishimura ,  Jun Iijima

IPC: G03F7/00

Abstract: According to one embodiment, an imprinting apparatus is provided. The imprinting apparatus includes a controller that controls a resist drop position on a wafer to be imprinted with a pattern, using a first resist drop recipe corresponding to a first topography of the wafer.

公开(公告)号：US20180261575A1

公开(公告)日：2018-09-13

申请号：US15706017

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi TAGAMI ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/08 ,  H01L25/50 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/08146 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US09887262B2

公开(公告)日：2018-02-06

申请号：US14837295

申请日：2015-08-27

Applicant: Toshiba Memory Corporation

Inventor： Yoshihiro Minami ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Masayoshi Tagami

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/06 ,  H01L23/532 ,  H01L29/788 ,  H01L29/66 ,  H01L23/522 ,  H01L27/11521

CPC classification number: H01L29/0649 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/11521 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788

Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.

公开(公告)号：US10950630B2

公开(公告)日：2021-03-16

申请号：US16927309

申请日：2020-07-13

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L25/065 ,  H01L23/00 ,  G11C16/26 ,  G11C5/02 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US10600771B2

公开(公告)日：2020-03-24

申请号：US16126018

申请日：2018-09-10

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun Iijima ,  Yumi Nakajima

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: In one embodiment, a semiconductor device includes a first interconnection including a first extending portion extending in a first direction, and a first curved portion curved with respect to the first extending portion. The device further includes a second interconnection including a second extending portion extending in the first direction and adjacent to the first extending portion in a second direction, and a second curved portion curved with respect to the second extending portion. The device further includes a first plug provided on the first curved portion, or on a first non-opposite portion included in the first extending portion and not opposite to the second extending portion in the second direction. The device further includes a second plug provided on the second curved portion, or on a second non-opposite portion included in the second extending portion and not opposite to the first extending portion in the second direction.