公开(公告)号：US11063062B2

公开(公告)日：2021-07-13

申请号：US16564783

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun Iijima ,  Masayoshi Tagami ,  Shinya Arai ,  Takahiro Tomimatsu

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/00

Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.

公开(公告)号：US10991719B2

公开(公告)日：2021-04-27

申请号：US16566036

申请日：2019-09-10

Applicant: Toshiba Memory Corporation

Inventor： Shinya Arai

IPC: H01L27/11582 ,  G11C16/04 ,  H01L21/28 ,  H01L49/02 ,  G11C16/26 ,  H01L27/11568 ,  H01L27/11553 ,  H01L27/11551

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

公开(公告)号：US10985181B2

公开(公告)日：2021-04-20

申请号：US16844026

申请日：2020-04-09

Applicant: Toshiba Memory Corporation

Inventor： Shinya Arai

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/764 ,  H01L29/06 ,  G11C16/14 ,  H01L27/11573 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/11529 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/225 ,  H01L29/167 ,  H01L21/02

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US10461092B2

公开(公告)日：2019-10-29

申请号：US15824396

申请日：2017-11-28

Applicant: Toshiba Memory Corporation

Inventor： Shinya Arai

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  H01L21/28 ,  H01L27/11568 ,  H01L49/02 ,  H01L27/11553 ,  H01L27/11551

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

公开(公告)号：US09881874B2

公开(公告)日：2018-01-30

申请号：US15057406

申请日：2016-03-01

Applicant: Toshiba Memory Corporation

Inventor： Kenichi Yasuda ,  Shinya Arai

IPC: H01L29/06 ,  H01L23/544 ,  H01L21/033 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/28 ,  H01L21/66 ,  H01L21/027

CPC classification number: H01L23/544 ,  G03F1/42 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/28282 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76877 ,  H01L22/20 ,  H01L27/11582 ,  H01L28/00 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.

公开(公告)号：US20200343264A1

公开(公告)日：2020-10-29

申请号：US16928113

申请日：2020-07-14

Applicant: Toshiba Memory Corporation

Inventor： Jun Fujiki ,  Shinya Arai ,  Kotaro Fujii

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L27/07 ,  H01L27/11573

Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.

公开(公告)号：US10804288B2

公开(公告)日：2020-10-13

申请号：US16137702

申请日：2018-09-21

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinya Arai

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

公开(公告)号：US20190355742A1

公开(公告)日：2019-11-21

申请号：US16296276

申请日：2019-03-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takayuki MARUYAMA ,  Yoshiaki Fukuzumi ,  Yuki Sugiura ,  Shinya Arai ,  Fumie Kikushima ,  Keisuke Suda ,  Takashi Ishida

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/768

Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.

公开(公告)号：US10319734B2

公开(公告)日：2019-06-11

申请号：US15001991

申请日：2016-01-20

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito Yoshimizu ,  Akifumi Gawase ,  Kei Watanabe ,  Shinya Arai

IPC: H01L27/11582 ,  H01L21/764 ,  H01L23/532

Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a second air gap, a first insulating film, a semiconductor film, and a stacked film. The stacked body is provided above the substrate and includes a plurality of electrode films stacked via a first air gap. The second air gap extends in a stacking direction of the stacked body. The second air gap separates the stacked body in a first direction crossing the stacking direction. The first insulating film is provided above the stacked body and covers an upper end of the second air gap. The stacked film is provided between a side surface of the electrode film and a side surface of the semiconductor film opposed to the side surface of the electrode film. The stacked film is in contact with the side surface of the electrode film and the side surface of the semiconductor film.

公开(公告)号：US10109643B2

公开(公告)日：2018-10-23

申请号：US15344021

申请日：2016-11-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Shinya Arai

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.