公开(公告)号：US10950630B2

公开(公告)日：2021-03-16

申请号：US16927309

申请日：2020-07-13

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L25/065 ,  H01L23/00 ,  G11C16/26 ,  G11C5/02 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US10811360B2

公开(公告)日：2020-10-20

申请号：US15061579

申请日：2016-03-04

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Masayoshi Tagami

IPC: H01L23/544 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an insulating film, a first interconnect, a conductor, and a frame-shaped portion. The insulating film is provided on the semiconductor layer. The first interconnect is provided on the insulating film. The conductor extends through the insulating film and electrically connects the semiconductor layer and the first interconnect. The frame-shaped portion extends through the insulating film and is provided in a second region different from a first region, the conductor being provided in the first region. The frame-shaped portion protrudes from a surface of the insulating film on which the first interconnect is provided.

公开(公告)号：US10297578B2

公开(公告)日：2019-05-21

申请号：US15706017

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US20200295037A1

公开(公告)日：2020-09-17

申请号：US16564783

申请日：2019-09-09

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun Iijima ,  Masayoshi Tagami ,  Shinya Arai ,  Takahiro Tomimatsu

IPC: H01L27/11582 ,  H01L23/00 ,  H01L23/522 ,  H01L27/11573

Abstract: In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.

公开(公告)号：US10741527B2

公开(公告)日：2020-08-11

申请号：US16390639

申请日：2019-04-22

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：US10510764B2

公开(公告)日：2019-12-17

申请号：US15948057

申请日：2018-04-09

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Toru Matsuda ,  Yu Hirotsu ,  Naoki Yamamoto

IPC: H01L27/115 ,  H01L21/288 ,  H01L21/768 ,  H01L23/528 ,  H01L29/792 ,  H01L23/498 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor device includes a stacked body, first, second, third, and fourth insulating bodies, first and second columnar portions. The stacked body includes a conductive layer and an insulating layer stacked alternately. The first, second, third and fourth insulating bodies, the first and second columnar portions are provided inside the stacked body. The second insulating body is at a position different from the first insulating body. The third insulating body is between the first and second insulating bodies. The fourth insulating body is between the first and second insulating bodies, and includes portions contacting the third insulating body and being separated from each other with the third insulating body interposed. The first columnar portion is between the first and fourth insulating bodies. The second columnar portion is between the second and fourth insulating bodies. The first and second columnar portions include a semiconductor layer.

公开(公告)号：US20190296035A1

公开(公告)日：2019-09-26

申请号：US16127962

申请日：2018-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Jun IIJIMA ,  Masayoshi Tagami ,  Takamasa Usui ,  Takahito Nishimura

IPC: H01L27/11578 ,  H01L27/11568 ,  G11C11/24

Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

公开(公告)号：US20200294971A1

公开(公告)日：2020-09-17

申请号：US16561658

申请日：2019-09-05

Applicant: Toshiba Memory Corporation

Inventor： Yusuke TANAKA ,  Atsushi Hieno ,  Tsutomu Nakanishi ,  Yasuhito Yoshimizu ,  Masayoshi Tagami

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.

公开(公告)号：US10748928B2

公开(公告)日：2020-08-18

申请号：US16707646

申请日：2019-12-09

Applicant: Toshiba Memory Corporation

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H01L27/11582 ,  H01L25/065 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/00 ,  G11C16/26 ,  G11C16/04 ,  G11C5/02

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US09887262B2

公开(公告)日：2018-02-06

申请号：US14837295

申请日：2015-08-27

Applicant: Toshiba Memory Corporation

Inventor： Yoshihiro Minami ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Masayoshi Tagami

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/06 ,  H01L23/532 ,  H01L29/788 ,  H01L29/66 ,  H01L23/522 ,  H01L27/11521

CPC classification number: H01L29/0649 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/11521 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/788

Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.