公开(公告)号：US20190326309A1

公开(公告)日：2019-10-24

申请号：US16128655

申请日：2018-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA ,  Shinya ARAI

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768

Abstract: A semiconductor memory device includes a substrate, a plurality of first electrode layers, a semiconductor layer, a plurality of second electrode layers, and a conductor. The plurality of first electrode layers are arranged to be separated from each other in a first direction above the substrate. The semiconductor layer extends through the plurality of first electrode layers in the first direction. The plurality of second electrode layers are arranged to be separated from each other in the first direction, arranged to be separated from the plurality of first electrode layers in a second direction crossing the first direction, and arranged at substantially the same levels as levels of the plurality of first electrode layers in the first direction. The conductor electrically connects the plurality of second electrode layers to each other. The plurality of second electrode layers are connected in parallel by the conductor.

公开(公告)号：US20190088588A1

公开(公告)日：2019-03-21

申请号：US15923488

申请日：2018-03-16

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumitaka ARAI ,  Satoshi NAGASHIMA

IPC: H01L23/528 ,  H01L27/11582 ,  H01L23/522

Abstract: A semiconductor memory device includes first and second insulating plates, a stacked body provided between the first insulating plate and the second insulating plate, and a semiconductor member. The stacked body includes interconnect layers. The interconnect layer includes a first interconnect portion contacting the first insulating plate, a second interconnect portion contacting the second insulating plate, a third interconnect portion, a fourth interconnect portion, fifth and sixth interconnect portions are separated from the first and the second insulating plates. The fifth interconnect portion is connected to the first interconnect portion via the third interconnect portion, and is insulated from the second interconnect portion. The sixth interconnect portion is connected to the second interconnect portion via the fourth interconnect portion, and is insulated from the first interconnect portion. The semiconductor member is disposed between the fifth interconnect portion and the sixth interconnect portion.