公开(公告)号：US20190333928A1

公开(公告)日：2019-10-31

申请号：US16298865

申请日：2019-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA ,  Keisuke NAKATSUKA ,  Fumitaka ARAI ,  Shinya ARAI ,  Yasuhiro UCHIYAMA

IPC: H01L27/11578 ,  H01L27/1157 ,  G11C11/40

Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.

公开(公告)号：US20170373082A1

公开(公告)日：2017-12-28

申请号：US15682996

申请日：2017-08-22

Applicant: Toshiba Memory Corporation

Inventor： Katsuyuki SEKINE ,  Tatsuya KATO ,  Fumitaka ARAI ,  Toshiyuki IWAMOTO ,  Yuta WATANABE ,  Wataru SAKAMOTO ,  Hiroshi ITOKAWA ,  Akio KANEKO

IPC: H01L27/11556 ,  H01L21/768 ,  H01L29/51 ,  H01L29/788 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/285 ,  H01L27/11519 ,  H01L29/10

CPC classification number: H01L27/11556 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76801 ,  H01L27/11519 ,  H01L29/1037 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/456 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/513 ,  H01L29/515 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889

Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.

公开(公告)号：US20200303400A1

公开(公告)日：2020-09-24

申请号：US16502877

申请日：2019-07-03

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumitaka ARAI ,  Masakazu GOTO ,  Masaki KONDO ,  Keiji HOSOTANI ,  Nobuyuki MOMO

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  H01L27/1157 ,  H01L27/11573

Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnecting layer; a first signal line; a first memory cell that stores first information between the first interconnecting layer and the first signal line; second to fourth interconnecting layers provided above the first interconnecting layer; fifth to seventh interconnecting layers disposed apart from the second to fourth interconnecting layers; a second signal line coupled to the first signal line; a third signal line coupled to the first and second signal lines and the sixth interconnecting layer; and, first to fifth transistors.

公开(公告)号：US20200090752A1

公开(公告)日：2020-03-19

申请号：US16296100

申请日：2019-03-07

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya KATO ,  Yusuke SHIMADA ,  Fumitaka ARAI

IPC: G11C16/04 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device of an embodiment includes a substrate, a first conductive layer provided above the substrate, the first conductive layer being spaced apart from the substrate in a first direction, and the first conductive layer being provided parallel to a substrate plane, a second conductive layer provided adjacent to the first conductive layer in a second direction intersecting the first direction, the second conductive layer being provided parallel to the substrate plane, a third conductive layer provided above the first conductive layer, the third conductive layer being spaced apart from the first conductive layer in the first direction, and the third conductive layer being provided parallel to the substrate plane, a fourth conductive layer provided above the second conductive layer, the fourth conductive layer being spaced apart from the second conductive layer in the first direction, and the fourth conductive layer being provided parallel to the substrate plane, a fifth conductive layer provided above the third conductive layer, the fifth conductive layer being spaced apart from the third conductive layer in the first direction, and the fifth conductive layer being provided parallel to the substrate plane, a sixth conductive layer provided above the fourth conductive layer, the sixth conductive layer being spaced apart from the fourth conductive layer in the first direction, and the sixth conductive layer being provided parallel to the substrate plane, an insulator provided between the first and second conductive layers, between the third and fourth conductive layers, and between the fifth and sixth conductive layers, a first signal line provided between the first, third, and fifth conductive layers and the insulator, the first signal line extending in the first direction, a second signal line provided between the second, fourth, and sixth conductive layers and the insulator, the second signal line extending in the first direction, a first memory cell provided between the first conductive layer and the first signal line, the first memory cell being configured to store first information, a second memory cell provided between the second conductive layer and the second signal line, the second memory cell being configured to store second information, a third memory cell provided between the third conductive layer and the first signal line, the third memory cell being configured to store third information, a fourth memory cell provided between the fourth conductive layer and the second signal line, the fourth memory cell being configured to store fourth information, a fifth memory cell provided between the fifth conductive layer and the first signal line, the fifth memory cell being configured to store fifth information, a sixth memory cell provided between the sixth conductive layer and the second signal line, the sixth memory cell being configured to store sixth information, and a control circuit configured to apply a second voltage to the third conductive layer, the control circuit being configured to apply a third voltage to the fifth conductive layer, the control circuit being configured to read data from the first memory cell, the second voltage being smaller than a first voltage, the first voltage being applied to the first conductive layer, and the third voltage being larger than the first voltage.

公开(公告)号：US20190088588A1

公开(公告)日：2019-03-21

申请号：US15923488

申请日：2018-03-16

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumitaka ARAI ,  Satoshi NAGASHIMA

IPC: H01L23/528 ,  H01L27/11582 ,  H01L23/522

Abstract: A semiconductor memory device includes first and second insulating plates, a stacked body provided between the first insulating plate and the second insulating plate, and a semiconductor member. The stacked body includes interconnect layers. The interconnect layer includes a first interconnect portion contacting the first insulating plate, a second interconnect portion contacting the second insulating plate, a third interconnect portion, a fourth interconnect portion, fifth and sixth interconnect portions are separated from the first and the second insulating plates. The fifth interconnect portion is connected to the first interconnect portion via the third interconnect portion, and is insulated from the second interconnect portion. The sixth interconnect portion is connected to the second interconnect portion via the fourth interconnect portion, and is insulated from the first interconnect portion. The semiconductor member is disposed between the fifth interconnect portion and the sixth interconnect portion.

公开(公告)号：US20180083022A1

公开(公告)日：2018-03-22

申请号：US15822860

申请日：2017-11-27

Applicant: Toshiba Memory Corporation

Inventor： Tatsuya KATO ,  Wataru SAKAMOTO ,  Fumitaka ARAI

IPC: H01L27/11556 ,  H01L27/11548 ,  H01L27/11519

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11548

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.

公开(公告)号：US20200176033A1

公开(公告)日：2020-06-04

申请号：US16562372

申请日：2019-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Keiji HOSOTANI ,  Fumitaka ARAI ,  Keisuke NAKATSUKA

IPC: G11C5/06 ,  H01L23/48 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.

公开(公告)号：US20180350829A1

公开(公告)日：2018-12-06

申请号：US16041460

申请日：2018-07-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsutomu TEZUKA ,  Fumitaka ARAI ,  Keiji IKEDA ,  Tomomasa UEDA ,  Nobuyoshi SAITO ,  Chika TANAKA ,  Kentaro MIURA ,  Tomoaki SAWABE

IPC: H01L27/11568 ,  G11C16/04 ,  G11C5/06 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11568 ,  G11C5/06 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

公开(公告)号：US20180331116A1

公开(公告)日：2018-11-15

申请号：US16041577

申请日：2018-07-20

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu TEZUKA ,  Fumitaka ARAI ,  Keiji IKEDA ,  Tomomasa UEDA ,  Nobuyoshi SAITO ,  Chika TANAKA ,  Kentaro MIURA ,  Tomoaki SAWABE

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C7/18 ,  G11C8/14

CPC classification number: H01L27/11578 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4234

Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.

公开(公告)号：US20210351235A1

公开(公告)日：2021-11-11

申请号：US17381911

申请日：2021-07-21

Applicant: Toshiba Memory Corporation

Inventor： Masahiro KIYOTOSHI ,  Akihito YAMAMOTO ,  Yoshio OZAWA ,  Fumitaka ARAI ,  Riichiro SHIROTA

IPC: H01L27/24 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L45/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/51

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.