公开(公告)号：US20200075622A1

公开(公告)日：2020-03-05

申请号：US16284128

申请日：2019-02-25

Applicant: Toshiba Memory Corporation

Inventor： Kotaro FUJII ,  Satoshi NAGASHIMA ,  Yumi NAKAJIMA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/8234 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.

公开(公告)号：US20200075615A1

公开(公告)日：2020-03-05

申请号：US16296001

申请日：2019-03-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Atsushi OGA ,  Hideaki HARAKAWA ,  Satoshi NAGASHIMA ,  Natsuki FUKUDA

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/762

Abstract: According to an embodiment, a semiconductor memory device includes: a first stacked body including a first semiconductor layer, a first memory film, a second semiconductor layer and a first insulating layer; a joining member provided on the first semiconductor layer, the second semiconductor layer, and the first insulating layer; a first layer provided above the joining member and covering the first semiconductor layer and the first memory film; a second layer provided above the joining member, located away from the first layer as viewed in a second direction perpendicular to the first direction, and covering the second semiconductor layer and the second memory film; a second stacked body including a third semiconductor layer, a fourth semiconductor layer, a fourth memory film and a second insulating layer.

公开(公告)号：US20190333928A1

公开(公告)日：2019-10-31

申请号：US16298865

申请日：2019-03-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA ,  Keisuke NAKATSUKA ,  Fumitaka ARAI ,  Shinya ARAI ,  Yasuhiro UCHIYAMA

IPC: H01L27/11578 ,  H01L27/1157 ,  G11C11/40

Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.

公开(公告)号：US20200098784A1

公开(公告)日：2020-03-26

申请号：US16297079

申请日：2019-03-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA ,  Fumitaka ARAI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/528 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768

Abstract: According to one embodiment, a semiconductor memory includes: a first member extending in a first direction perpendicular to a surface of a substrate, and including a first semiconductor layer; first and second interconnects extending in a second direction parallel to the surface of the substrate, the second interconnect neighboring the first interconnect in a third direction; a second member extending in the first direction and above the first member, the second member including a second semiconductor layer; third and a fourth interconnects extending in the second direction, the fourth interconnect neighboring the third interconnect in the third direction; and a third semiconductor layer between the first and the second members, the third semiconductor layer being continuous with the first and the second semiconductor layers.

公开(公告)号：US20200286902A1

公开(公告)日：2020-09-10

申请号：US16518030

申请日：2019-07-22

Applicant: Toshiba Memory Corporation

Inventor： Natsuki FUKUDA ,  Satoshi NAGASHIMA ,  Tetsu MOROOKA ,  Noritaka ISHIHARA

IPC: H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/06 ,  H01L21/311 ,  H01L21/764 ,  H01L21/28

Abstract: According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.

公开(公告)号：US20190296040A1

公开(公告)日：2019-09-26

申请号：US16122258

申请日：2018-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kotaro FUJII ,  Masahisa SONODA ,  Masaru KITO ,  Satoshi NAGASHIMA ,  Shigeki KOBAYASHI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/14 ,  G11C16/08

Abstract: A semiconductor device according to an embodiment includes first conductors, first pillars, a pillar column. Each of the first pillars is provided through the first conductors. The pillar column includes second pillars that are aligned in a first direction. Each of the second pillars is provided through the first conductors. The pillar column includes first and second columns of the second pillars. The first and second columns of the second pillars are aligned in a second direction that intersects the first direction. The first pillars are arranged on both sides in the second direction of each pillar column. The first conductors are provided continuously on both sides in the second direction of the second pillars that are included in each pillar column.

公开(公告)号：US20180083018A1

公开(公告)日：2018-03-22

申请号：US15688826

申请日：2017-08-28

Applicant: Toshiba Memory Corporation

Inventor： Shigehiro YAMAKITA ,  Yoshiaki FUKUZUMI ,  Wataru SAKAMOTO ,  Satoshi NAGASHIMA

IPC: H01L27/11517 ,  H01L27/1157 ,  H01L27/105 ,  H01L27/11524 ,  H01L29/788

CPC classification number: H01L27/11517 ,  H01L27/1052 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/788

Abstract: A semiconductor memory device includes a semiconductor substrate, a stepped structure including a stepped part in which a plurality of first insulating layers and conductive layers are alternately stacked on a main surface of the semiconductor substrate, the conductive layers including first, second, and third conductive layers, a second insulating layer which covers the stepped structure, a first contact interconnection which penetrates the second insulating layer and the first conductive layer in a thickness direction of the semiconductor substrate and is electrically connected to the second conductive layer, and a second contact interconnection which penetrates the second insulating layer and the second conductive layer in the thickness direction of the semiconductor substrate and is electrically connected to the third conductive layer.

公开(公告)号：US20180006051A1

公开(公告)日：2018-01-04

申请号：US15706559

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Satoshi NAGASHIMA ,  Tatsuya KATO

IPC: H01L27/11556 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11521

CPC classification number: H01L27/11556 ,  G11C16/0483 ,  G11C16/10 ,  H01L21/76885 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/7889

Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

公开(公告)号：US20210288057A1

公开(公告)日：2021-09-16

申请号：US17331147

申请日：2021-05-26

Applicant: Toshiba Memory Corporation

Inventor： Satoshi NAGASHIMA ,  Tatsuya KATO ,  Wataru SAKAMOTO

IPC: H01L27/11556 ,  G11C16/04 ,  G11C16/10 ,  H01L29/788 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11521

Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

公开(公告)号：US20200091181A1

公开(公告)日：2020-03-19

申请号：US16294728

申请日：2019-03-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L21/28 ,  H01L29/423

Abstract: A semiconductor memory device comprises: stacked bodies adjacent to each other in a second direction, each comprising conductive layers stacked in a first direction; semiconductor portions arranged in a third direction between the stacked bodies, and comprising semiconductor layers facing the conductive layers, and a first insulating layer; and a second insulating layer provided between the semiconductor portions. The smallest distance from a geometrical center of gravity of the second insulating layer to the stacked body on a predetermined first cross-section being represented by D1; a distance from surfaces of the stacked bodies facing the semiconductor portion on a predetermined second cross-section being represented by D2, the relationship 2D1>D2 is satisfied.