公开(公告)号：US20200286990A1

公开(公告)日：2020-09-10

申请号：US16510488

申请日：2019-07-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhiro UCHIYAMA ,  Shinya ARAI ,  Koichi SAKATA ,  Takahiro TOMIMATSU

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/761

Abstract: A semiconductor device including a first chip and a second chip. The first chip includes: a first substrate; a first transistor that is provided on the first substrate; and a first pad that is provided above the first transistor and that is electrically connected to the first transistor. The second chip includes: a second pad that is provided on the first pad; a second substrate that is provided above the second pad and that includes a first diffusion layer and a second diffusion layer, at least one of the first diffusion layer and the second diffusion layer being electrically connected to the second pad; and an isolation insulating film or an isolation trench that extends at least from an upper surface of the second substrate to a lower surface of the second substrate within the second substrate and that isolates the first diffusion layer from the second diffusion layer.

公开(公告)号：US20200006381A1

公开(公告)日：2020-01-02

申请号：US16566036

申请日：2019-09-10

Applicant: Toshiba Memory Corporation

Inventor： Shinya ARAI

IPC: H01L27/11582 ,  G11C16/04 ,  H01L21/28 ,  G11C16/26 ,  H01L27/11568

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

公开(公告)号：US20180323213A1

公开(公告)日：2018-11-08

申请号：US16040292

申请日：2018-07-19

Applicant: Toshiba Memory Corporation

Inventor： Shinya ARAI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/764 ,  H01L29/06 ,  G11C16/14

CPC classification number: H01L27/11582 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/14 ,  H01L21/0217 ,  H01L21/2257 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0649 ,  H01L29/167

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US20210043546A1

公开(公告)日：2021-02-11

申请号：US17079736

申请日：2020-10-26

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yoshiro SHIMOJO ,  Shinya ARAI

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

公开(公告)号：US20200235125A1

公开(公告)日：2020-07-23

申请号：US16844026

申请日：2020-04-09

Applicant: Toshiba Memory Corporation

Inventor： Shinya ARAI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/764 ,  H01L29/06 ,  G11C16/14 ,  H01L27/11573 ,  H01L27/11556

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US20190326309A1

公开(公告)日：2019-10-24

申请号：US16128655

申请日：2018-09-12

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Satoshi NAGASHIMA ,  Shinya ARAI

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768

Abstract: A semiconductor memory device includes a substrate, a plurality of first electrode layers, a semiconductor layer, a plurality of second electrode layers, and a conductor. The plurality of first electrode layers are arranged to be separated from each other in a first direction above the substrate. The semiconductor layer extends through the plurality of first electrode layers in the first direction. The plurality of second electrode layers are arranged to be separated from each other in the first direction, arranged to be separated from the plurality of first electrode layers in a second direction crossing the first direction, and arranged at substantially the same levels as levels of the plurality of first electrode layers in the first direction. The conductor electrically connects the plurality of second electrode layers to each other. The plurality of second electrode layers are connected in parallel by the conductor.

公开(公告)号：US20190027494A1

公开(公告)日：2019-01-24

申请号：US16138619

申请日：2018-09-21

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/11582 ,  H01L29/423 ,  H01L27/11565 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11575

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20220115403A1

公开(公告)日：2022-04-14

申请号：US17559786

申请日：2021-12-22

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takayuki MARUYAMA ,  Yoshiaki FUKUZUMI ,  Yuki SUGIURA ,  Shinya ARAI ,  Fumie KIKUSHIMA ,  Keisuke SUDA ,  Takashi ISHIDA

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L21/768

Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.

公开(公告)号：US20200335517A1

公开(公告)日：2020-10-22

申请号：US16918005

申请日：2020-07-01

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20200075461A1

公开(公告)日：2020-03-05

申请号：US16678007

申请日：2019-11-08

Applicant: Toshiba Memory Corporation

Inventor： Yasuhito YOSHIMIZU ,  Yoshiro SHIMOJO ,  Shinya ARAI

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11565

Abstract: According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.