Abstract:
A plasma display device includes a plasma display panel (PDP). A chassis base supports the PDP from a surface of the same opposite a surface that displays images, and a plurality of driving circuit boards are mounted on the chassis base. A front cabinet is positioned adjacent to the surface of the plasma display panel that displays images. Also, a back cover is positioned adjacent to a surface of the chassis base opposite the surface adjacent to the PDP and is integrally assembled to the front cabinet with the chassis base and the plasma display panel interposed therebetween. The plasma display device also includes thermoelectric semiconductor devices that are mounted within the back cover. The thermoelectric semiconductor devices act to discharge heat generated by the PDP and the driving circuit boards to outside the back cover.
Abstract:
A plasma display panel includes first and second substrates spaced apart from each other at a distance while proceeding substantially parallel to each other. The first and the second substrates have a display area and a non-display area. A plurality of address electrodes are formed on the first substrate, and covered by a dielectric layer. Main barrier ribs are arranged between the substrates to form discharge cells. Phosphor layer is formed with the discharge cells. A plurality of discharge sustain electrodes are formed on the surface of the second substrate facing the first substrate, and covered by a dielectric layer. Reinforcing barrier ribs are arranged at the non-display area while surrounding the display area, and connected to the main barrier ribs with an outer structure curved toward the outside of the substrates.
Abstract:
A Plasma Display Panel (PDP) includes: a front substrate and a rear substrate facing each other; a plurality of barrier ribs arranged between the front substrate and the rear substrate, defining a plurality of discharge cells where a discharge occurs, and including a plurality of recesses; a plurality of electrodes corresponding to the discharge cells and adapted to generate the discharge; a plurality of phosphor layers arranged within the discharge cells; and a discharge gas contained within the discharge cells.
Abstract:
A plasma display device includes a plate member arranged at a distance from a circuit substrate to allow air to pass between the plate member and the circuit substrate. The plate member includes an extension arranged at an angle to the plate member to deflect heat generated by the driving circuits through a hole in the plasma display device cover.
Abstract:
A plasma display panel including an upper substrate and a lower substrate facing each other; barrier ribs arranged between the upper and lower substrates to define a plurality of discharge cells together with the upper and lower substrates; a discharge sustain electrode pair extending along discharge cells arranged in a first direction, and including a scan electrode and a sustain electrode arranged in parallel with each other; a floating electrode arranged between the scan electrode and the sustain electrode and electrically floated; an address electrode extending in a second direction of crossing the first direction; a phosphor layer arranged in the discharge cells; and a discharge gas filled in the discharge cells.
Abstract:
Breakage of an IC included in a plasma display device can be prevented by a plasma display device including: a Plasma Display Panel (PDP); a chassis base attached the PDP on one side thereof and attached to a printed circuit board assembly on another side thereof; an Integrated Circuit (IC) package including an IC coupled between an electrode from the PDP and the printed circuit board assembly; and a cover plate attached to a chassis base interposing the IC package; and at least one of the chassis base and the cover plate includes at least one slit arranged in a vicinity of a portion corresponding to the IC.
Abstract:
A plasma display panel capable of preventing faulty discharge and non-uniform discharge by applying a uniform address voltage to all subpixels. This is done by neutralizing the negative surface potential of a zinc silicate green fluorescent material using YBO3:Tb as a positive surface potential material on the partition walls between the electrodes. Also, the thickness of this YBO3:Tb material and a lateral spacing between a scan electrode and the positive surface potential material are carefully selected to arrive at a design resulting in no faulty pixels. Grooves can also be formed in the tops of the partition walls so that the positive surface potential material filled therein does not mix with the neighboring flourescent material.
Abstract:
A PDP includes a barrier rib formed between an upper substrate and a lower substrate to define discharge regions, and a phosphor layer including red, green, and blue phosphor layers corresponding to the discharge regions. A height of the green phosphor layer is lower than a height of the barrier rib.
Abstract:
A plasma display panel (PDP) is characterized such that the strength of barrier ribs can be maintained, impurity gases can be easily exhausted, and a discharge gas can be smoothly filled in the discharge cells when manufacturing the PDP. The PDP includes: a transparent front substrate; a rear substrate disposed facing the front substrate; a plurality of discharge electrodes disposed between the front substrate and the rear substrate; a plurality of barrier ribs disposed between the front substrate and the rear substrate, and defining a plurality of discharge cells which are spaces for generating a discharge, the barrier ribs having side walls that define an exhaust channel formed in at least a portion between the discharge cells, at least one of the side walls having an arc-like shape; a phosphor layer disposed in each of the discharge cells; and a discharge gas filled in the discharge cells.
Abstract:
A Plasma Display Panel (PDP) includes: a front substrate, a common electrode and a scan electrode arranged on a lower surface of the front substrate, a bus electrode electrically connected to the common electrode and the scan electrode, a front dielectric layer covering the common electrode, the scan electrode, and the bus electrode, a rear substrate facing the front substrate, an address electrode arranged on an upper surface of the rear substrate to cross the bus electrode, a barrier rib arranged between the front and rear substrates, and a phosphor layer arranged on a discharge space defined by the barrier rib. The bus electrode includes a display unit bus electrode arranged on a display area that displays pixels, and a non-display unit bus electrode arranged on a non-display area electrically connected to the display unit bus electrode and connected to an external terminal. The display unit bus electrode and the non-display unit bus electrode have different structures. The non-display unit bus electrode arranged on the non-display area is a single-layered structure while the display unit bus electrode arranged on the display area is a double-layered structure.