公开(公告)号：US20210226121A1

公开(公告)日：2021-07-22

申请号：US17221674

申请日：2021-04-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Sheng-Chih LAI ,  Han-Ting TSAI ,  Chung-Te LIN

IPC: H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02

Abstract: A device includes a conductive feature, a dielectric layer, a bottom electrode via, and a liner layer. The dielectric layer is over the conductive feature. The bottom electrode via is in the dielectric layer and over the conductive feature. A topmost surface of the bottom electrode via is substantially flat. A liner layer cups an underside of the bottom electrode via. The liner layer has a topmost end substantially level with the topmost surface of the bottom electrode via.

公开(公告)号：US20200266338A1

公开(公告)日：2020-08-20

申请号：US16866101

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Sheng-Chih LAI ,  Han-Ting TSAI ,  Chung-Te LIN

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22

Abstract: A method for fabricating a memory device is provided. The method includes depositing a resistance switching element layer over a bottom electrode layer; depositing a top electrode layer over the resistance switching element layer; etching the top electrode layer, the resistance switching element layer, and the bottom electrode layer to form a memory stack; depositing a first spacer layer over the memory stack and; etching the first spacer layer to form a first spacer extending along a sidewall of the memory stack; depositing a second spacer layer over the memory stack and the first spacer; etching the second spacer layer to form a second spacer extending along a sidewall of the first spacer; and depositing an etch stop layer over and in contact with a top of the second spacer, wherein the etch stop layer is spaced apart from the first spacer by a portion of the second spacer.

公开(公告)号：US20190148633A1

公开(公告)日：2019-05-16

申请号：US16122179

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Ren DAI ,  Chung-Ju LEE ,  Chung-Te LIN ,  Chih-Wei LU ,  Hsi-Wen TIEN ,  Tai-Yen PENG ,  Chien-Min LEE ,  Wei-Hao LIAO

IPC: H01L43/12 ,  H01L27/22

Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

公开(公告)号：US20190131524A1

公开(公告)日：2019-05-02

申请号：US15799416

申请日：2017-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Han-Ting TSAI ,  Jyu-Horng SHIEH ,  Chung-Te LIN

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/02

Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.