公开(公告)号：US20190252610A1

公开(公告)日：2019-08-15

申请号：US16397871

申请日：2019-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Han-Ting TSAI ,  Jyu-Horng SHIEH ,  Chung-Te LIN

IPC: H01L45/00 ,  H01L43/02 ,  H01L27/24

CPC classification number: H01L45/148 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L43/02 ,  H01L43/12 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1675

Abstract: A memory device includes an inter-layer dielectric (ILD) layer, a metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a bottom electrode via. The metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer. The memory cell is over the metal-containing compound layer and includes a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The bottom electrode via connects the bottom electrode to the metallization pattern through the metal-containing compound layer and the etch stop layer.

公开(公告)号：US20190165258A1

公开(公告)日：2019-05-30

申请号：US15828101

申请日：2017-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Sheng-Chih LAI ,  Han-Ting TSAI ,  Chung-Te LIN

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16

Abstract: A method for fabricating a memory device includes forming a resistance switching element over a bottom electrode; forming a top electrode over the resistance switching element; forming a first spacer covering a sidewall of the resistance switching element; forming a second spacer surrounding the first spacer and exposing the top electrode; and forming a metallization pattern connected with the top electrode and the second spacer.

公开(公告)号：US20230210028A1

公开(公告)日：2023-06-29

申请号：US18170947

申请日：2023-02-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Han-Ting TSAI ,  Jyu-Horng SHIEH ,  Chung-Te LIN

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20

CPC classification number: H10N70/884 ,  H10B61/22 ,  H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/023 ,  H10N70/24 ,  H10N70/063 ,  H10N70/245 ,  H10N70/826 ,  H10N70/8416 ,  H10N70/8833

Abstract: An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

公开(公告)号：US20210343937A1

公开(公告)日：2021-11-04

申请号：US17369671

申请日：2021-07-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Han-Ting TSAI ,  Jyu-Horng SHIEH ,  Chung-Te LIN

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.

公开(公告)号：US20200266339A1

公开(公告)日：2020-08-20

申请号：US16866106

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Sheng-Chih LAI ,  Han-Ting TSAI ,  Chung-Te LIN

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22

Abstract: A memory device includes a bottom electrode, a resistance switching element, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching element is over the bottom electrode. The capping layer is over the resistance switching element. The top electrode is over the capping layer. The first spacer extends along a sidewall of the resistance switching element. The second spacer extends along a sidewall of the first spacer and beyond a top of the first spacer, in which the second spacer is in contact with the capping layer.

公开(公告)号：US20230276712A1

公开(公告)日：2023-08-31

申请号：US18312372

申请日：2023-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Sheng-Chih LAI ,  Han-Ting TSAI ,  Chung-Te LIN

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  H10B61/20 ,  H10N50/10 ,  H10N50/80

Abstract: A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.

公开(公告)号：US20200235292A1

公开(公告)日：2020-07-23

申请号：US16840100

申请日：2020-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pin-Ren DAI ,  Chung-Ju LEE ,  Chung-Te LIN ,  Chih-Wei LU ,  Hsi-Wen TIEN ,  Tai-Yen PENG ,  Chien-Min LEE ,  Wei-Hao LIAO

IPC: H01L43/12

Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MU) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

公开(公告)号：US20190157344A1

公开(公告)日：2019-05-23

申请号：US15966639

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Hsien WEI ,  Chung-Te LIN ,  Han-Ting TSAI ,  Tai-Yen PENG ,  Pin-Ren DAI ,  Chien-Min LEE ,  Sheng-Chih LAI ,  Wei-Chih WEN

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

公开(公告)号：US20250093762A1

公开(公告)日：2025-03-20

申请号：US18434528

申请日：2024-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lee-Feng CHEN ,  Yen-Liang CHEN ,  Chien-Min LEE ,  Kuo Lun TAI ,  Shy-Jay LIN

IPC: G03F1/24

Abstract: An EUV lithography mask including a substrate, a patterned absorber layer including a first material and a second material. In some embodiments, the first material is a second row transition metal and the second material is a first row transition metal or second row transition metal. The disclosed EUV lithography masks reduce undesirable mask 3D effects.

公开(公告)号：US20240206344A1

公开(公告)日：2024-06-20

申请号：US18595256

申请日：2024-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Sheng-Chih LAI ,  Han-Ting TSAI ,  Chung-Te LIN

IPC: H10N50/01 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/01 ,  G11C11/161 ,  H10B61/20 ,  H10N50/10 ,  H10N50/80

Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.