公开(公告)号：US20210328031A9

公开(公告)日：2021-10-21

申请号：US16729704

申请日：2019-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gulbagh SINGH ,  Tsung-Han TSAI ,  Kun-Tsang CHUANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: The present disclosure relates to a semiconductor structure includes a substrate with a top surface and first and second devices formed on the top surface of the substrate. The semiconductor structure also includes a deep isolation structure formed in the substrate and between the first and second devices. The deep isolation structure includes a top portion formed at the top surface and having a top width and a bottom surface having a bottom width larger than the top width.

公开(公告)号：US20200006560A1

公开(公告)日：2020-01-02

申请号：US16117064

申请日：2018-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gulbagh SINGH ,  Hsin-Chi CHEN ,  Kun-Tsang CHUANG

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/02

Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

公开(公告)号：US20190393078A1

公开(公告)日：2019-12-26

申请号：US16014103

申请日：2018-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gulbagh SINGH ,  Hsin-Chi Chen ,  Kun-Tsang Chuang

IPC: H01L21/762 ,  H01L27/12

Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.

公开(公告)号：US20190164987A1

公开(公告)日：2019-05-30

申请号：US16035251

申请日：2018-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gulbagh SINGH ,  Chen-Hao LI ,  Chih-Ming LEE ,  Chi-Yen LIN ,  Cheng-Tsu LIU

IPC: H01L27/11568

Abstract: The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.

公开(公告)号：US20190148385A1

公开(公告)日：2019-05-16

申请号：US16020855

申请日：2018-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Gulbagh SINGH ,  Shun-Chi TSAI ,  Chih-Ming LEE ,  Chi-Yen LIN ,  Kuo-Hung LO

IPC: H01L27/11 ,  H01L29/423 ,  H01L29/06 ,  G11C11/412

Abstract: An integrated circuit structure includes a semiconductor substrate, an active area, a gate electrode, and a butted contact. The active area is oriented in a first direction and has at least one tooth portion extending in a second direction in the semiconductor substrate. The gate electrode overlies the active area and extends in the second direction. The butted contact has a first portion above the gate electrode and a second portion above the active area. A portion of the second portion of the butted contact lands on the tooth portion.