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    Method for forming a bulk semiconductor substrate configured to exhibit soi behavior
    1.
    发明授权
    Method for forming a bulk semiconductor substrate configured to exhibit soi behavior 有权

    公开(公告)号：US11211283B2

    公开(公告)日：2021-12-28

    申请号：US16889425

    申请日：2020-06-01

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Gulbagh Singh ,  Kun-Tsang Chuang ,  Hsin-Chi Chen

    IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/10 ,  H01L21/265 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

    摘要： Bulk semiconductor substrates configured to exhibit semiconductor-on-insulator (SOI) behavior, and corresponding methods of fabrication, are disclosed herein. An exemplary bulk substrate configured to exhibit SOI behavior includes a first isolation trench that defines a channel region of the bulk substrate and a second isolation trench that defines an active region that includes the channel region. The first isolation trench includes a first isolation trench portion and a second isolation trench portion disposed over the first isolation trench portion. A first isolation material fills the first isolation trench portion, and an epitaxial material fills the second isolation trench portion. The epitaxial material is disposed on the first isolation material. A second isolation material fills the second isolation trench. A portion of the bulk substrate underlying the first isolation trench and the channel region is configured to have a higher resistance than the bulk substrate.

    Shallow trench isolation for integrated circuits
    2.
    发明授权
    Shallow trench isolation for integrated circuits 有权

    公开(公告)号：US11145539B2

    公开(公告)日：2021-10-12

    申请号：US16657446

    申请日：2019-10-18

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Gulbagh Singh ,  Hsin-Chi Chen ,  Kun-Tsang Chuang

    IPC分类号： H01L29/76 ,  H01L21/762 ,  H01L27/12

    摘要： The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.

    Source/drain epitaxial layer profile
    4.
    发明授权
    Source/drain epitaxial layer profile 有权

    公开(公告)号：US10790391B2

    公开(公告)日：2020-09-29

    申请号：US16117064

    申请日：2018-08-30

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Gulbagh Singh ,  Hsin-Chi Chen ,  Kun-Tsang Chuang

    IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/265

    摘要： The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

    Isolation regions for reduced junction leakage
    5.
    发明申请
    Isolation regions for reduced junction leakage 审中-公开

    公开(公告)号：US20200058736A1

    公开(公告)日：2020-02-20

    申请号：US15998405

    申请日：2018-08-15

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Gulbagh Singh ,  Hsin-Chi Chen ,  Kun-Tsang Chuang

    IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8234

    摘要： The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.

    REDUCING RC DELAY IN SEMICONDUCTOR DEVICES
    9.
    发明公开
    REDUCING RC DELAY IN SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230378071A1

    公开(公告)日：2023-11-23

    申请号：US18361560

    申请日：2023-07-28

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Gulbagh SINGH ,  Kun-Tsang Chuang ,  Po-Jen Wang

    IPC分类号： H01L23/535 ,  H01L21/74 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L23/535 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/7682 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/4821

    摘要： The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.