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    SOURCE/DRAIN EPITAXIAL LAYER PROFILE
    1.
    发明申请
    SOURCE/DRAIN EPITAXIAL LAYER PROFILE 有权

    公开(公告)号：US20220359751A1

    公开(公告)日：2022-11-10

    申请号：US17815063

    申请日：2022-07-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gulbagh SINGH ,  Hsin-Chi CHEN ,  Kun-Tsang CHUANG

    IPC: H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/265

    Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

    ISOLATION REGIONS FOR REDUCED JUNCTION LEAKAGE
    2.
    发明申请
    ISOLATION REGIONS FOR REDUCED JUNCTION LEAKAGE 审中-公开

    公开(公告)号：US20200251554A1

    公开(公告)日：2020-08-06

    申请号：US16855914

    申请日：2020-04-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gulbagh SINGH ,  Hsin-Chi CHEN ,  Kun-Tsang CHUANG

    IPC: H01L29/06 ,  H01L21/306 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/02

    Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.

    SRAM STRUCTURE
    3.
    发明申请
    SRAM STRUCTURE 审中-公开

    公开(公告)号：US20200381441A1

    公开(公告)日：2020-12-03

    申请号：US16994900

    申请日：2020-08-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Gulbagh SINGH ,  Shun-Chi TSAI ,  Chih-Ming LEE ,  Chi-Yen LIN ,  Kuo-Hung LO

    IPC: H01L27/11 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

    Abstract: An SRAM structure includes first and second gate strips extending along a first direction. A first active region extends across the first gate strip from a top view, and forms a first pull-up transistor with the first gate strip. A second active region extends across the second gate strip from the top view, and forms a second pull-up transistor with the second gate strip. From the top view the first active region has a first stepped sidewall facing away from the second active region. The first stepped sidewall has a first side surface farthest from the second active region, a second side surface set back from the first side surface along the first direction, and a third side surface set back from the second side surface along the first direction.

    REDUCING RC DELAY IN SEMICONDUCTOR DEVICES
    4.
    发明公开
    REDUCING RC DELAY IN SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230378071A1

    公开(公告)日：2023-11-23

    申请号：US18361560

    申请日：2023-07-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gulbagh SINGH ,  Kun-Tsang Chuang ,  Po-Jen Wang

    IPC: H01L23/535 ,  H01L21/74 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/7682 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/4821

    Abstract: The present disclosure describes a method for reducing RC delay in radio frequency operated devices or devices that would benefit from an RC delay reduction. The method includes forming, on a substrate, a transistor structure having source/drain regions and a gate structure; depositing a first dielectric layer on the substrate to embed the transistor structure; forming, within the first dielectric layer, source/drain contacts on the source/drain regions of the transistor structure; depositing a second dielectric layer on the first dielectric layer; forming metal lines in the second dielectric layer; forming an opening in the second dielectric layer between the metal lines to expose the first dielectric layer; etching, through the opening, the second dielectric layer between the metal lines and the first dielectric layer between the source/drain contacts; and depositing a third dielectric layer to form an air-gap in the first and second dielectric layers and over the transistor structure.

    Shallow Trench Isolation for Integrated Circuits
    5.
    发明申请
    Shallow Trench Isolation for Integrated Circuits 审中-公开

    公开(公告)号：US20200051851A1

    公开(公告)日：2020-02-13

    申请号：US16657446

    申请日：2019-10-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gulbagh SINGH ,  Hsin-Chi Chen ,  Kun-Tsang Chuang

    IPC: H01L21/762 ,  H01L27/12

    Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.

    METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH METAL SILICIDE LAYER
    6.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH METAL SILICIDE LAYER 审中-公开

    公开(公告)号：US20200044035A1

    公开(公告)日：2020-02-06

    申请号：US16179165

    申请日：2018-11-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gulbagh SINGH ,  Cheng-Yeh HUANG ,  Chin-Nan CHANG ,  Chih-Ming LEE ,  Chi-Yen LIN

    IPC: H01L29/40 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L29/45 ,  H01L21/768

    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.

    Source/Drain Epitaxial Layer Profile
    10.
    发明申请
    Source/Drain Epitaxial Layer Profile 有权

    公开(公告)号：US20210013343A1

    公开(公告)日：2021-01-14

    申请号：US17031530

    申请日：2020-09-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gulbagh SINGH ,  Hsin-Chu CHEN ,  Kun-Tsang CHUANG

    IPC: H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/265

    Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

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