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    SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210407947A1

    公开(公告)日：2021-12-30

    申请号：US16917640

    申请日：2020-06-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hsin-Chi CHEN ,  Hsun-Ying HUANG ,  Chih-Ming LEE ,  Shang-Yen WU ,  Chih-An YANG ,  Hung-Wei HO ,  Chao-Ching CHANG ,  Tsung-Wei HUANG

    IPC: H01L23/00 ,  H01L21/768 ,  H01L23/488

    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a substrate having one or more devices formed thereon, one or more bonding pads disposed over the substrate, and a first passivation layer disposed over the one or more bonding pads. The first passivation layer includes a first passivation sublayer having a first dielectric material, a second passivation sublayer disposed over the first passivation sublayer, and the second passivation sublayer has a second dielectric material different from the first dielectric material. The first passivation layer further includes a third passivation sublayer disposed over the second passivation sublayer, and the third passivation sublayer has a third dielectric material different from the second dielectric material. At least two of the first, second, and third passivation sublayers each includes a nitride.

    METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH METAL SILICIDE LAYER
    3.
    发明申请
    METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH METAL SILICIDE LAYER 审中-公开

    公开(公告)号：US20200044035A1

    公开(公告)日：2020-02-06

    申请号：US16179165

    申请日：2018-11-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gulbagh SINGH ,  Cheng-Yeh HUANG ,  Chin-Nan CHANG ,  Chih-Ming LEE ,  Chi-Yen LIN

    IPC: H01L29/40 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L29/45 ,  H01L21/768

    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.

    SRAM STRUCTURE
    4.
    发明申请
    SRAM STRUCTURE 审中-公开

    公开(公告)号：US20200381441A1

    公开(公告)日：2020-12-03

    申请号：US16994900

    申请日：2020-08-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Gulbagh SINGH ,  Shun-Chi TSAI ,  Chih-Ming LEE ,  Chi-Yen LIN ,  Kuo-Hung LO

    IPC: H01L27/11 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

    Abstract: An SRAM structure includes first and second gate strips extending along a first direction. A first active region extends across the first gate strip from a top view, and forms a first pull-up transistor with the first gate strip. A second active region extends across the second gate strip from the top view, and forms a second pull-up transistor with the second gate strip. From the top view the first active region has a first stepped sidewall facing away from the second active region. The first stepped sidewall has a first side surface farthest from the second active region, a second side surface set back from the first side surface along the first direction, and a third side surface set back from the second side surface along the first direction.

    MEMORY DEVICE WITH IMPROVED DATA RETENTION
    9.
    发明申请
    MEMORY DEVICE WITH IMPROVED DATA RETENTION 审中-公开

    公开(公告)号：US20190164987A1

    公开(公告)日：2019-05-30

    申请号：US16035251

    申请日：2018-07-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Gulbagh SINGH ,  Chen-Hao LI ,  Chih-Ming LEE ,  Chi-Yen LIN ,  Cheng-Tsu LIU

    IPC: H01L27/11568

    Abstract: The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.

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