公开(公告)号：US20230063032A1

公开(公告)日：2023-03-02

申请号：US17976317

申请日：2022-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/11 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  H01L29/161 ,  G11C11/419 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/3213

Abstract: An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.

公开(公告)号：US20220384303A1

公开(公告)日：2022-12-01

申请号：US17884272

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L23/367 ,  H01L29/66 ,  H01L29/78 ,  H01L23/48 ,  H01L27/092 ,  H01L29/417

Abstract: An IC structure includes a plurality of first fins, a plurality of second fins, a plurality of first gate structures, a plurality of second gate structures, and a first gate contact. The first fins and the second fins are over a substrate. The first gate structures traverse the plurality of first fins. The second gate structures traverse the plurality of second fins. The first gate structures have a first gate pitch. The second gate structures have a second gate pitch wider than the first gate pitch. The first gate contact is over a first one of the second gate structures. The first gate contact overlaps a location where the first one of the second gate structures traverses across a first one of the second fins.

公开(公告)号：US20220246523A1

公开(公告)日：2022-08-04

申请号：US17725091

申请日：2022-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/092 ,  H01L21/768

Abstract: A semiconductor structure includes a channel region of a transistor in a semiconductor fin, source and drain regions of the transistor on the semiconductor fin and at opposite sides of the channel region, a gate of the transistor over the channel region, and a first metal structure. The first metal structure is disposed over a first one of the source and drain regions. The first metal structure includes a first portion lower than a top surface of the gate, a second portion higher than the top surface of the gate, and a third portion over the second portion, wherein the second portion is narrower than the first portion, and the third portion is wider than the second portion.

公开(公告)号：US20210367037A1

公开(公告)日：2021-11-25

申请号：US17398278

申请日：2021-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/417 ,  H01L27/088

Abstract: An integrated circuit (IC) structure includes a first cell and a second cell abutting the first cell. The first cell includes a first fin-like field-effect transistor (FinFET). The first FinFET includes a first channel region in a first fin extending along a first direction, and a first gate electrode extending across the first channel region in the first fin along a second direction different from the first direction. The second FinFET includes a second channel region in a second fin aligned with the first fin along the first direction, and a second gate electrode extending across the second channel region in the second fin along the second direction. The second fin has a smaller width than the first fin.

公开(公告)号：US20210098466A1

公开(公告)日：2021-04-01

申请号：US16589273

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first dielectric fin, a first semiconductor fin and a second dielectric fin over a substrate. The first semiconductor fin is between the first dielectric fin and the second dielectric fin. The semiconductor structure also includes a first gate electrode wrapping the first dielectric fin, a channel region of the first semiconductor fin and the second dielectric fin and a first source/drain structure over a source/drain portion of the first semiconductor fin, being in contact with and interposing the first dielectric fin and the second dielectric fin.

公开(公告)号：US20210057421A1

公开(公告)日：2021-02-25

申请号：US16548313

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a plurality of memory cells arranged in a cell array over the substrate. Each of the memory cells includes a latch circuit, a pass-gate transistor, and an isolation transistor. The latch circuit is formed by two cross-coupled inverters. The pass-gate transistor is coupled between an output terminal of the latch circuit and a bit line. The isolation transistor includes a drain and a gate, both coupled to the output terminal of the latch circuit, and a source that is floating. A first gate length of the isolation transistor is greater than a second gate length of the pass-gate transistor and a plurality of transistors within the latch circuit.

公开(公告)号：US20200335585A1

公开(公告)日：2020-10-22

申请号：US16388404

申请日：2019-04-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/10 ,  H01L27/11 ,  H01L27/092 ,  H01L23/528 ,  H01L21/74 ,  H01L21/8238

Abstract: An integrated circuit device includes a substrate, a fin field-effect transistor (FinFET), and a well strap. The substrate has a first doped region of a first type dopant. The FinFET is over the doped region and includes a first semiconductor fin and a first source/drain region in the first semiconductor fin, in which the first source/drain region is of a second type dopant that has a different conductivity type than the first type dopant. The well strap is over the doped region, includes a second semiconductor fin and a second source/drain region in the second semiconductor fin, in which the second source/drain region is of the first type dopant. A width of the second semiconductor fin is greater than a width of the first semiconductor fin.

公开(公告)号：US20200328216A1

公开(公告)日：2020-10-15

申请号：US16383957

申请日：2019-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit formed by two cross-coupled inverters, and a pass-gate transistor coupling an output of the latch circuit to a bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact. The logic cell includes a transistor. A second source/drain region of the transistor is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact. The first and second vias are the same height. The interconnect line and the bit line are formed in the same metal layer, and the bit line is thicker than the interconnect line.

公开(公告)号：US20200105768A1

公开(公告)日：2020-04-02

申请号：US16247840

申请日：2019-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L27/11 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L29/08 ,  G11C8/14 ,  G11C7/18

Abstract: Semiconductor structures are provided. A memory cell includes a latch circuit formed by two cross-coupled inverters and a pass-gate transistor coupling an output of the latch circuit to a bit line. Each cross-coupled inverter is connected to a VDD line of a first metallization layer. A word line of a second metallization layer is connected to a gate of the pass-gate transistor through a first via over the gate of the pass-gate transistor, a first landing pad of the first metallization layer, and a second via over the first landing pad. A source/drain region of the pass-gate transistor is connected to the bit line of a third metallization layer through a contact over the source/drain region, a third via over the contact, a continuous via-plug over the third via, and a fourth via over the continuous via-plug. The continuous via-plug penetrates the first and second metallization layers.

公开(公告)号：US20200105612A1

公开(公告)日：2020-04-02

申请号：US16211949

申请日：2018-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ta-Chun LIN ,  Tien-Shao CHUANG ,  Kuang-Cheng TAI ,  Chun-Hung CHEN ,  Chih-Hung HSIEH ,  Kuo-Hua PAN ,  Jhon-Jhy LIAW

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region and a second well region that have different conductivity types and are adjacent to each other. A first fin structure protrudes from the semiconductor substrate and is formed in the first well region. A second fin structure protrudes from the semiconductor substrate and is formed in the second well region and adjacent to the first fin structure. A first multi-step isolation structure that includes a first isolation portion is formed between the first fin structure and the second fin structure. A second isolation portion extends from the bottom surface of the first isolation portion. The second isolation portion has a top width that is narrower than the bottom width of the first isolation portion.