公开(公告)号：US20210159326A1

公开(公告)日：2021-05-27

申请号：US16882014

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  Ling-Sung Wang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

公开(公告)号：US20240363734A1

公开(公告)日：2024-10-31

申请号：US18770088

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  Ling-Sung Wang

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/28088 ,  H01L21/76877 ,  H01L21/82345 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

公开(公告)号：US20240347614A1

公开(公告)日：2024-10-17

申请号：US18752321

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ying Hsin Lu ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ling-Sung Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/40 ,  H01L29/786

CPC classification number: H01L29/42376 ,  H01L27/088 ,  H01L29/404 ,  H01L29/42392 ,  H01L29/78696

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiment. The semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. The second transistors are high-frequency transistors and the first transistors are logic transistors.

公开(公告)号：US12113120B2

公开(公告)日：2024-10-08

申请号：US17813814

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  Ling-Sung Wang

IPC: H01L29/08 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/28088 ,  H01L21/76877 ,  H01L21/82345 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

公开(公告)号：US20220359728A1

公开(公告)日：2022-11-10

申请号：US17813814

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Ching-Hwanq Su ,  Pin Chia Su ,  Ying Hsin Lu ,  Ling-Sung Wang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.