公开(公告)号：US11437516B2

公开(公告)日：2022-09-06

申请号：US15381270

申请日：2016-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Szu-Chi Yang ,  Chih-Hsiang Huang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165

Abstract: A semiconductor structure includes a gate structure disposed over a substrate, and a plurality of source/drain features disposed on the substrate and interposed by the gate structure. Each of the source/drain features includes a first doped source/drain region extended away from the substrate, and a second doped source/drain region disposed on top and side surfaces of the first doped source/drain region, in which a phosphorus doping concentration of the first doped source/drain region is lower than a doping concentration of the second doped source/drain region.

公开(公告)号：US20210098311A1

公开(公告)日：2021-04-01

申请号：US16938340

申请日：2020-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

IPC: H01L21/8238 ,  H01L27/11 ,  H01L21/306

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

公开(公告)号：US20180151737A1

公开(公告)日：2018-05-31

申请号：US15381270

申请日：2016-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Szu-Chi Yang ,  Chih-Hsiang Huang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165

Abstract: A semiconductor structure includes a gate structure disposed over a substrate, and a plurality of source/drain features disposed on the substrate and interposed by the gate structure. Each of the source/drain features includes a first doped source/drain region extended away from the substrate, and a second doped source/drain region disposed on top and side surfaces of the first doped source/drain region, in which a phosphorus doping concentration of the first doped source/drain region is lower than a doping concentration of the second doped source/drain region.